US 8,552,779 B2 · Synchronizer latch circuit that facilitates resolving metastability

Abstract

The disclosed embodiments provide a synchronizer latch circuit that facilitates resolving metastability issues. This synchronizer latch circuit includes a set of lightly loaded, cross-coupled transistors that form a metastable resolving and state-holding element that is coupled to two outputs. An incoming synchronization signal creates a voltage difference between the two outputs, but does not directly force a state change for the outputs. Instead, the data and clock inputs control transistors that allow neighboring power sources and/or ground network connections to weakly influence the outputs. The cross-coupled transistors then amplify the resulting voltage difference to generate valid output voltages, even when the data input and clock signal are received at roughly the same time. Thus, the synchronizer latch circuit facilitates rapidly resolving metastability and improving synchronizer performance.

Claims20

Dependent claims

A synchronizer latch circuit that facilitates resolving metastability, comprising:

a data input;
a clock input;
a first output;
a second output;
a set of two or more cross-coupled transistors, wherein the gate of a first cross-coupled transistor is coupled to the second output, the gate of a second cross-coupled transistor is coupled to the first output, the drain of the first cross-coupled transistor is coupled to the first output, and the drain of the second cross-coupled transistor is coupled to the second output;
and
a third transistor, wherein the data input is coupled to the gate of the third transistor;
wherein, upon receiving a synchronization signal, the data input activates the third transistor to change a voltage of the first output and create a voltage difference between the first output and the second output, and wherein the cross-coupled transistors amplify the voltage difference to generate valid logic output voltages even when the data input arrives within a setup-and-hold time window of the synchronizer latch circuit.

5 more elements

A computing device, comprising:

a transmitting component that operates in a first clock domain;
and
a receiving component that operates in a second clock domain;
wherein the receiving component includes a synchronizer latch circuit that facilitates resolving metastability, wherein the synchronizer latch circuit comprises:
a data input that receives a synchronization signal from the transmitting component;
a clock input;
a first output;
a second output;
a set of two or more cross-coupled transistors, wherein the gate of a first cross-coupled transistor is coupled to the second output, the gate of a second cross-coupled transistor is coupled to the first output, the drain of the first cross-coupled transistor is coupled to the first output, and the drain of the second cross-coupled transistor is coupled to the second output;
and
a third transistor, wherein the data input is coupled to the gate of the third transistor;
wherein, upon receiving the synchronization signal, the data input activates the third transistor to change a voltage of the first output and create a voltage difference between the first output and the second output, and wherein the cross-coupled transistors amplify the voltage difference to generate valid logic output voltages even when the data input arrives within a setup-and-hold time window of the synchronizer latch circuit.

9 more elements

Dependencies are inferred from the claim text.

Synchronizer latch circuit that facilitates resolving metastability

Life of this patent

Synchronizer latch circuit that facilitates resolving metastability

Life of this patent

Abstract

Claims20