Duty cycle corrector and duty cycle correction method

A method of generating from an input clock signal an output clock signal having a desired duty cycle, comprising:

• generating from the input clock signal a pulsed clock signal, by converting rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle multiplied by a clock period;
• and
• generating from the pulsed clock signal the output clock signal, by delaying falling edges of the pulsed clock signal by a controlled delay, wherein generating from the pulsed clock signal further comprises a control stage, wherein the control stage comprises
• a CMOS inverter comprising a first PMOS transistor for outputting a high and a first NMOS transistor for outputting a low, and
• a second transistor, wherein the second transistor is selected from the group consisting of a PMOS transistor, and an NMOS transistor, wherein a second transistor coupled between a source of the first PMOS transistor and a high bias potential when the second transistor is the PMOS transistor, wherein a rise time of the control stage is a function of a gate-to-source voltage at the second transistor, otherwise the second transistor coupled between a source of the first NMOS transistor and a low bias potential when the second transistor is the NMOS transistor, wherein a fall time of the control stage is a function of the gate-to-source voltage at the second transistor.

A duty cycle corrector for generating from an input clock signal an output clock signal having a desired duty cycle, comprising:

• a duty cycle detector for generating a control signal as a function of a duty cycle of the output clock signal;
• a pulse generating stage for generating from the input clock signal a pulsed clock signal, the pulse generating stage converting rising edges of the input clock signal into pulses, each of which pulses is shorter than the desired duty cycle multiplied by a clock period;
• a pulse stretching stage for generating from the pulsed clock signal the output clock signal, the pulse stretching stage delaying falling edges of the pulsed clock signal by a controlled delay, wherein the pulse stretching stage comprises a control stage, wherein the control stage comprises
• a CMOS inverter comprising a first PMOS transistor and a first NMOS transistor, and
• a second transistor, wherein the second transistor is selected from the group consisting of a PMOS transistor, and an NMOS transistor, wherein the second transistor coupled between a source of the first PMOS transistor and a high bias potential when the second transistor is the PMOS transistor, otherwise the second transistor coupled between a source of the first NMOS transistor and a low bias potential when the second transistor is the NMOS transistor;
• and
• a feedback path for delivering the control signal to the pulse stretching stage, wherein the control signal coupled to a gate of the second transistor of the control stage.