Back to results
US 8,552,774 B2Granted
Fast-switching low-noise charge pump
AssigneeQUALCOMM Incorporated
InventorsShen Wang, Sang-Oh Lee, Jeongsik Yang
Life of this patent
Estimating the term…
Abstract
In one embodiment of the invention, a method for a charge pump is disclosed. The method includes biasing a plurality of transistors; switching a pair of main transistor switches to apply or remove a net charge on an output terminal though the biased transistors; and turning on auxiliary transistor switches when the main transistor switches are turned off. The auxiliary transistor switches when turned on provide an auxiliary equalizing path to nodes between the main transistor switches and the biased transistors. The auxiliary equalizing path equalizes voltages between the intermediate nodes to rapidly turn off the biased transistors and reduce noise on the output terminal of the charge pump.
Claims19
A circuit comprising:
- a voltage controlled oscillator to generate an output clock signal of variable frequency in response to a direct current control voltage;
- a frequency divider coupled to the voltage controlled oscillator, the frequency divider configured to divide down a frequency of the output clock signal to generate a frequency divided output signal;
- a phase frequency detector coupled to the frequency divider and configured to compare a phase and frequency of a reference clock signal with a phase and frequency of the frequency divided output signal to generate frequency control signals;
- and
- a charge pump configured to generate an output control voltage based on the frequency control signals, the charge pump having a first auxiliary switching transistor and a second auxiliary switching transistor that are coupled in series between a first intermediate node of a plurality of series coupled transistors and a second intermediate node of the plurality of series coupled transistors, the first auxiliary switching transistor and the second auxiliary switching transistor to switch on to provide an equalization path between the first intermediate node and the second intermediate node to reduce noise in the output of the charge pump, wherein the charge pump further includes:
- a biased transistor having a terminal coupled to the first intermediate nodes;
- a gate terminal coupled to an output of an operational amplifier;
- a first main switching transistor having a first terminal coupled to a positive power supply and a second terminal coupled to the first intermediate node;
- a second main switching transistor coupled to ground;
- and
- a second biased transistor coupled between a charge pump output terminal of the charge pump and the second main switching transistor, wherein a second terminal of the biased transistor is coupled to the charge pump output terminal of the charge pump, and wherein the first main switching transistor and the second main switching transistor are configured to charge the charge pump output terminal of the charge pump.
8 more elements
An apparatus comprising:
- means for generating an output clock signal based on a direct current control voltage;
- means for dividing down a frequency of the output clock signal to generate a frequency divided output signal;
- means for detecting a phase and frequency by comparing a phase and frequency of a reference clock signal with a phase and frequency of the frequency divided output signal to generate frequency control signals;
- and
- means for generating an output control voltage based on the frequency control signals, the means for generating the output control voltage comprising a first auxiliary switching transistor and a second auxiliary switching transistor that are coupled in series between a first intermediate node of a plurality of series coupled transistors and a second intermediate node of the plurality of series coupled transistors, the first auxiliary switching transistor and the second auxiliary switching transistor configured to switch on to provide an equalization path between the first intermediate node and the second intermediate node, wherein the means for generating the output control voltage further includes:
- a biased transistor having a terminal coupled to the first intermediate nodes;
- a gate terminal coupled to an output of an operational amplifier;
- a first main switching transistor having a first terminal coupled to a positive power supply and a second terminal coupled to the first intermediate node;
- a second main switching transistor coupled to ground;
- and
- a second biased transistor coupled between an output terminal of the means for generating the output control voltage and the second main switching transistor, wherein a second terminal of the biased transistor is coupled to the output terminal of the means for generating the output control voltage, and wherein the first main switching transistor and the second main switching transistor are configured to charge the output terminal of the means for generating the output control voltage.
8 more elements
A method comprising:
- generating an output clock signal based on a direct current control voltage;
- dividing down a frequency of the output clock signal to generate a frequency divided output signal;
- detecting a phase and frequency of the frequency divided output signal by comparing a phase and frequency of a reference clock signal with the phase and frequency of the frequency divided output signal to generate frequency control signals;
- and
- generating, by a charge pump, an output control voltage based on the frequency control signals, the charge pump comprising a first auxiliary switching transistor and a second auxiliary switching transistor that are coupled in series between a first intermediate node of a plurality of series coupled transistors and a second intermediate node of the plurality of series coupled transistors, the first auxiliary switching transistor and the second auxiliary switching transistor configured to switch on to provide an equalization path between the first intermediate node and the second intermediate node, wherein the charge pump further includes:
- a biased transistor having a terminal coupled to the first intermediate nodes;
- a gate terminal coupled to an output of an operational amplifier;
- a first main switching transistor having a first terminal coupled to a positive power supply and a second terminal coupled to the first intermediate node;
- a second main switching transistor coupled to ground;
- and
- a second biased transistor coupled between a charge pump output terminal of the charge pump and the second main switching transistor, wherein a second terminal of the biased transistor is coupled to the charge pump output.
8 more elements
Dependencies are inferred from the claim text.