Frequency divider with synchronous range extension across octave boundaries
AssigneeCoherent Logix, Incorporated
InventorMark S. Cavin
Life of this patent
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Abstract
A frequency divider based on a series of divide-by-2/3 cells and divide-by-1/2/3 cells using extended division range is disclosed. The frequency divider uses modified divide-by-1/2/3 cells and additional circuit elements to correctly divide an input frequency by a divisor on successive output cycles while the divisor transitions across an octave boundary. The frequency divider creates a divide-by-1 mode for unused divide-by-1/2/3 cells in the series of cells. The divide-by-1 mode passes the input clock in the unused latches of each unused divide-by-1/2/3 cell as opposed to having each unused divide-by-1/2/3 cell implement divide-by-3 mode.
Claims20
A frequency divider comprising a series of one or more divide-by-2/3 cells and one or more divide-by-1/2/3 cells, wherein the frequency divider is configured to correctly divide an input frequency by a divisor on successive output cycles, responsive to the divisor transitioning across an octave boundary on the successive output cycles, and wherein a last divide-by-1/2/3 cell of the series is configured to utilize a synchronous divide-by-1 mode responsive to the divisor transitioning across the octave boundary, wherein synchronous divide-by-1 mode entails passing an input clock through a D node of a first latch of the last divide-by-1/2/3 cell.
A frequency divider comprising a series of one or more divide-by-2/3 cells and one or more divide-by-1/2/3 cells using extended division range, wherein the frequency divider is configured to:
- divide an input frequency by a divisor value;
- move the divisor value across an octave boundary on consecutive output cycles without suffering from a discontinuity;
- and
- utilize a synchronous divide-by-1 responsive to the divisor value transitioning across the octave boundary, wherein synchronous divide-by-1 entails passing an input clock through a D node of a first latch of a last divide-by-1/2/3 cell of the series.
A circuit comprising:
- one or more divide-by-2/3 cells;
- and
- one or more divide-by-1/2/3 cells coupled to the one or more divide-by-2/3 cells;
- wherein the circuit is configured to:
- receive an input programming word, wherein the input programming word represents a divisor value and takes on one of a plurality of positive integer values;
- divide an input frequency by the divisor value;
- and
- responsive to the divisor value transitioning across an octave boundary on successive output cycles, correctly generate an output frequency on the successive output cycles, wherein the output frequency is equal to an input frequency divided by the divisor value.
Dependencies are inferred from the claim text.