Systems, circuits, and methods for a digital frequency synthesizer

A method, comprising:

• receiving a phase error signal;
• generating, by a time to digital converter (TDC), a digital TDC output signal based on the phase error signal;
• combining the digital TDC output signal with a digital ramp offset signal to provide a loop filter input signal, the digital ramp offset signal having a phase that ramps from approximately 0 to approximately π;
• filtering the loop filter input signal in a loop filter to provide one or more control signals;
• and
• generating an output clock based on the one or more control signals.

A frequency synthesizer system, comprising:

• a time to digital converter (TDC) configured to provide a digital TDC output signal based on a phase error signal;
• a summer configured to combine a ramp offset signal with the digital TDC output signal;
• and
• a voltage-controlled oscillator (VCO), coupled to the summer, configured to provide an output clock having a frequency that is based on a slope of the ramp offset signal.