Clock glitch detection circuit
AssigneeFreescale Semiconductor, Inc.
InventorsMichael Rohleder, Thomas Koch, Vladimir Litovtchenko, Thomas Luedeke
Life of this patent
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Abstract
In a first circuit for detecting clock glitches in a clock signal, a master counter is clocked by the clock signal and memorizes a master count. An incrementer advances the master count by one increment. A slave counter is clocked by the clock signal and memorizes a slave count. The slave count is retarded relative to the master count by at least a particular number of clock edges. A comparator determines whether the difference between the master count and the slave count is at least a value of the incrementer times the particular number of clock edges.
Claims20
A circuit for detecting clock glitches in a clock signal, comprising
- a master counter clocked by the clock signal configured to store a master count NM;
- an incrementer configured to advance the master count by one increment;
- a slave counter clocked by the clock signal configured to store a slave count Ns, wherein
- the slave count is retarded relative to the master count by at least P clock edges based on an input of the slave counter being coupled to an output of the master counter, and
- the number P is greater than or equal to one;
- and
- a comparator configured to determine whether a difference NM−NS between the master count and the slave count is at least P times the increment.
A method for detecting clock glitches in a clock signal, comprising:
- storing a master count NM at a master counter clocked by the clock signal;
- advancing the master count by one increment;
- storing a slave count NS at a slave counter clocked by the clock signal, wherein
- the slave count is retarded relative to the master count by at least P clock edges based on an input of the slave counter being coupled to an output of the master counter, and
- the number P is greater than or equal to one;
- and
- determining whether a difference NM−NS between the master count and the slave count is at least P times the increment.
A circuit for detecting clock glitches in a clock signal, comprising
- a master counter clocked by the clock signal configured to store a master count NM;
- an incrementer configured to advance the master count by one increment, wherein the incrementer includes:
- an incrementer input port to receive an input number;
- and
- an incrementer output port to deliver an output number, wherein the output number is the input number advanced by one increment, and an output of the master counter is coupled to the incrementer input port and the incrementer output port is coupled to an input port of the master counter;
- a slave counter clocked by the clock signal configured to store a slave count NS, wherein the slave count is retarded relative to the master count by at least P clock edges based on an input of the slave counter being coupled to the output of the master counter, and the number P is greater than or equal to one;
- and
- a comparator configured to determine whether a difference NM−Ns between the master count and the slave count is at least P times the increment.
Dependencies are inferred from the claim text.