US 8,552,763 B2Granted

Switch array including active regions being adjacent to each other in channel width direction of memory cell transistor

AssigneeKabushiki Kaisha Toshiba

InventorKeiko Abe

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Abstract

According to one embodiment, a switch array includes first and second switches provided in a switch unit. The first switch includes first and second memory cell transistors and a first pass transistor. A second switch includes third and fourth memory cell transistors and a second pass transistor. The first and second memory cell transistor is provided in a first active region. The first pass transistor is provided in a second active region in the substrate. The third and fourth memory cell transistor is provided in the first active region. The second pass transistor is provided in the second active region adjacent to the first pass transistor in the channel length direction. The first and second active regions are adjacent to each other in a channel width direction.

Claims20

Dependent claims

A switch array comprising:

a switch unit provided on a substrate, including;
a first switch provided in the switch unit and including first and second memory cell transistors and a first pass transistor,
the first memory cell transistor provided in a first active region in the substrate and including a first source, a first drain, and a first gate,
the second memory cell transistor provided in the first active region adjacent to the first memory cell transistor in a channel length direction of the first memory cell transistor and including the first drain shared with the first memory cell transistor, a second source, and a second gate, and
the first pass transistor provided in a second active region in the substrate and including a second drain, a third source, and a third gate connected to the first drain;
and
a second switch provided in the switch unit and including third and fourth memory cell transistors and a second pass transistor,
the third memory cell transistor provided in the first active region adjacent to the second memory cell transistor in the channel length direction of the first memory cell transistor and including the second source shared with the second memory cell transistor, a third drain, and a fourth gate,
the fourth memory cell transistor provided in the first active region adjacent to the third memory cell transistor in the channel length direction of the first memory cell transistor and including the third drain shared with the third memory cell transistor, a fourth source, and a fifth gate, and
the second pass transistor provided in the second active region adjacent to the first pass transistor in the channel length direction of the first pass transistor and including a fourth drain, a fifth source, and a sixth gate connected to the third drain,
wherein the first and second active regions are adjacent to each other in a channel width direction of each transistor.

8 more elements

A switch array comprising:

a switch unit provided on a substrate, including;
a first control line;
a first switch provided in the switch unit and including a first memory cell transistor and a first pass transistor,
the first memory cell transistor provided in a first active region in the substrate and including a first source connected to the first control line, a first drain, and a first gate, and
the first pass transistor provided in a second active region in the substrate and including a second source, a second drain, and a second gate connected to the first drain;
and
a second switch provided in the switch unit and including a second memory cell transistor and a second pass transistor,
the second memory cell transistor provided in the first active region adjacent to the first memory cell transistor in a channel length direction of a transistor and including the first source shared with the first memory cell transistor, a third drain, and a third gate, and
the second pass transistor provided in the second active region and including a third source, the second drain shared with the first pass transistor, and a fourth gate connected to the third drain,
wherein the first and second active regions are adjacent to each other in a channel width direction of each transistor.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/206,730Filed 10 Aug 2011
Priority: JP 2010-21583627 Sep 2010
Published: US 2012/0074467 A129 Mar 2012
Granted: 8 Oct 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification5 codes

H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 43/10
EEPROM devices comprising charge-trapping gate insulators: characterised by the top-view layout
H10B 43/30
EEPROM devices comprising charge-trapping gate insulators: characterised by the memory core region