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US 8,552,740 B2Granted
Method of measuring delay in an integrated circuit
AssigneeMaxeler Technologies Ltd.
InventorsPeter Ying Kay Cheung, Nicholas Peter Sedcole, Justin Sung-Jit Wong
Life of this patent
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Abstract
A method of measuring signal delay in a integrated circuit comprising applying a common clock signal at a circuit input and output, applying a test signal at the circuit input, detecting a corresponding output signal at the circuit output and detecting whether the test signal and output signal occur in a common part of the clock signal.
Claims26
A method of measuring signal delay in an integrated circuit comprising:
- applying a clock signal at a first register input and a second register input,
- applying a test signal to an input of the first register, wherein an output signal S from the first register is input to a circuit under test, and wherein an output signal D from the circuit under test is input into the second register, based on an output signal from the second register and the output signal D, detecting whether the output signal S and output signal D occur in a common part of the clock signal.
An apparatus for measuring signal delay in an integrated circuit comprising
- a first register;
- a second register;
- a clock signal generator configured to apply a common clock signal at a first register input and a second register input, wherein an output signal S from the first register is configured to be applied as input to a circuit under test, and wherein an output signal D from the circuit under test is configured to be applied as input into the second register, a test signal generator configured to apply a test signal to an input of the first register, and a detector configured to detect whether the output signal S applied at the input and an output signal D detected at the output fall in the common part of the clock signal.
Dependencies are inferred from the claim text.