Stacked semiconductor device including ESD protection circuits and method of fabricating the stacked semiconductor device

A stacked semiconductor device, comprising:

• a first semiconductor die that includes a front side electrically coupled to a substrate pad, the substrate pad being connected to an exterior, a backside of the first semiconductor die, a first integrated circuit, first electrostatic discharge protection circuits (ESDs), and through-silicon-vias (TSVs), the TSVs being coupled to the first integrated circuit and the first ESDs;
• a second semiconductor die that includes a second integrated circuit and second ESDs, the second integrated circuit being stacked above the backside of the first semiconductor die and being electrically connected to the TSVs, the second ESDs being electrically disconnected from the TSVs;
• and
• an interposer substrate coupled to the substrate pad,
• wherein the TSVs penetrate the first semiconductor die and extend to the backside of the first semiconductor die.

A method of fabricating a stacked semiconductor device, the method comprising:

• forming a first semiconductor die, the first semiconductor die including at least one first electro static discharge protection circuit (ESD), at least one through-silicon-via (TSV), and a first integrated circuit that are electrically connected to each other;
• forming a second semiconductor die, the second semiconductor die being stacked on the first semiconductor die to form a stacked structure, and the second semiconductor die including at least one second ESD and a second integrated circuit;
• and
• performing a fusing operation with respect to the second semiconductor die to cut off an electrical connection between the at least one second ESD and the at least one TSV.