Chip package and method for forming the same
OwnerYu-Lin Yen, Chien-Hui Chen +2inventors
InventorsYu-Lin Yen, Chien-Hui Chen, Tsang-Yu Liu, Long-Sheng Yeou
Life of this patent
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OwnerYu-Lin Yen, Chien-Hui Chen +2inventors
InventorsYu-Lin Yen, Chien-Hui Chen, Tsang-Yu Liu, Long-Sheng Yeou
Estimating the term…
A chip package includes a substrate having an upper surface and a lower surface, a plurality of conducting pads located under the lower surface of the substrate, and a dielectric layer located between the conducting pads. A hole is provided in the substrate, which extends from the upper surface towards the lower surface of the substrate. A sidewall or a bottom of the hole exposes a portion of the conducting pads. The upper opening of the hole near the upper surface is smaller than a lower opening of the hole near the lower surface. An upper conducting pad has at least an opening or a trench exposing a lower conducting pad of the conducting pads. A conducting layer is disposed in the hole, which electrically contacting at least one of the conducting pads.
A chip package, comprising:
A chip package, comprising:
A chip package, comprising:
Dependencies are inferred from the claim text.