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US 8,552,564 B2Granted
Hybrid-core through holes and vias
AssigneeIntel Corporation
InventorsMihir K. Roy, Islam Salama, Yonggang Li
Life of this patent
Estimating the term…
Abstract
A semiconductor device substrate includes a front section and back section that are laminated cores disposed on a front- and back surfaces of a first core. The first core has a cylindrical plated through hole that has been metal plated and filled with air-core material. The front- and back sections have laser-drilled tapered vias that are filled with conductive material and that are coupled to the plated through hole. The back section includes an integral inductor coil that communicates to the front section. The first core and the laminated-cores form a hybrid-core semiconductor device substrate with an integral inductor coil.
Claims23
A semiconductor device substrate, comprising:
- a first core with a front surface and a back surface;
- a laminated-core substrate built on the first core front- and back surfaces, wherein the laminated-core substrate includes a front section and a back section, wherein the front section includes couplings for a plurality of processors, and wherein at least one coupling communicates inductor-altered current from the integral inductor coil, and wherein the back section includes an integral inductor coil;
- wherein the first core includes a plated through hole (PTH) and front- and back PTH conductive pads in contact with the PTH, and wherein the PTH is an air core PTH;
- wherein the laminated-core substrate includes a tapered via in each of the front- and back sections that expose the PTH conductive pads and that include front- and back tapered contacts that contact the PTH conductive pad and that each include conductive pads coupled to the front- and back tapered vias.
1 more element
A semiconductor device substrate, comprising:
- a first core with a front surface and a back surface;
- a laminated-core substrate built on the first core front- and back surfaces, wherein the laminated-core substrate includes a front section and a back section, and wherein the back section includes an integral inductor coil, and wherein the back section includes at least three laminated layers, and wherein two of the at least three laminated layers are shunted together
- wherein the first core includes a plated through hole (PTH) and front- and back PTH conductive pads in contact with the PTH, and wherein the PTH is an air core PTH;
- wherein the laminated-core substrate includes a tapered via in each of the front- and back sections that expose the PTH conductive pads and that include front- and back tapered contacts that contact the PTH conductive pad and that each include conductive pads coupled to the front- and back tapered vias.
1 more element
A semiconductor device substrate, comprising:
- a first core with a front surface and a back surface;
- a laminated-core substrate built on the first core front- and back surfaces, wherein the laminated-core substrate includes a front section and a back section, wherein the front section includes a first plurality of laminated-core layers, wherein the back section includes a second plurality of laminated-core layers, and wherein the first plurality is less than the second plurality, and wherein the back section includes an integral inductor coil;
- wherein the first core includes a plated through hole (PTH) and front- and back PTH conductive pads in contact with the PTH, and wherein the PTH is an air core PTH;
- wherein the laminated-core substrate includes a tapered via in each of the front- and back sections that expose the PTH conductive pads and that include front- and back tapered contacts that contact the PTH conductive pad and that each include conductive pads coupled to the front- and back tapered vias.
1 more element
A computing system, comprising:
- a first core with a front surface and a back surface;
- a laminated -core substrate built on the first core front- and back surfaces, wherein the laminated-core substrate includes a front section and a back section, wherein the front section includes couplings for a plurality of processors, and wherein the back section includes an integral inductor coil;
- wherein the first core includes a plated through hole (PTH)and front- and back PTH conductive pads in contact with the PTH, and wherein the PTH is an air core PTH;
- wherein the laminated-core substrate includes a tapered via in each of the front- and back sections that expose the PTH conductive pads and that include front- and back tapered contacts that contact the PTH conductive pad and that each include conductive pads coupled to the front- and back tapered vias;
- wherein at least one coupling communicates inductor-altered current from the integral inductor coil;
- and
- a foundation substrate coupled to the integral inductor coil.
4 more elements
Dependencies are inferred from the claim text.