Back to results
US 8,552,559 B2Granted
Very thick metal interconnection scheme in IC chips
AssigneeMegica Corporation
InventorsMou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou
Life of this patent
Estimating the term…
Abstract
A new interconnection scheme is described, comprising both coarse and fine line interconnection schemes in an IC chip. The coarse metal interconnection, typically formed by selective electroplating technology, is located on top of the fine line interconnection scheme. It is especially useful for long distance lines, clock, power and ground buses, and other applications such as high Q inductors and bypass lines. The fine line interconnections are more appropriate to be used for local interconnections. The combined structure of coarse and fine line interconnections forms a new interconnection scheme that not only enhances IC speed, but also lowers power consumption.
Claims88
An integrated circuit chip comprising:
- a semiconductor substrate;
- multiple transistors in and on said semiconductor substrate;
- an insulating layer over said semiconductor substrate;
- a first metallization structure over said insulating layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a metal line comprising a copper portion, and said first metallization structure further comprises a first adhesion layer under said copper portion and at sidewalls of said metal line, wherein said metal line has a thickness less than 2 micrometers;
- a dielectric layer between said first and second metal layers;
- a first insulating nitride layer over said first metallization structure and over said dielectric layer;
- a second metallization structure on and in physical contact with a top surface of said first insulating nitride layer, wherein said second metallization structure comprises a second adhesion layer on said first insulating nitride layer, and an electroplated copper layer over said second adhesion layer, wherein said second adhesion layer physically contacts said top surface of said first insulating nitride layer, wherein said second adhesion layer is under said electroplated copper layer, but is not at sidewalls of said electroplated copper layer, wherein said electroplated copper layer has a thickness greater than 3 micrometers;
- a separating layer on said second metallization structure and on and in physical contact with said top surface of said first insulating nitride layer, wherein said separating layer physically contacts a top surface of said electroplated copper layer and said sidewalls of said electroplated copper layer, wherein said separating layer comprises a second insulating nitride layer over said top surface of said electroplated copper layer and over said top surface of said first insulating nitride layer;
- and
- a polymer layer on said separating layer, wherein an opening through said polymer layer and said separating layer is over a contact point of said top surface of said electroplated copper layer, and said contact point is at a bottom of said opening.
7 more elements
An integrated circuit chip comprising:
- a semiconductor substrate;
- multiple transistors in and on said semiconductor substrate;
- an insulating layer over said semiconductor substrate;
- a first metallization structure over said insulating layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a metal line comprising a copper portion, and said first metallization structure further comprises a first adhesion layer under said copper portion and at sidewalls of said metal line, wherein said metal line has a thickness less than 2 micrometers;
- a dielectric layer between said first and second metal layers;
- an insulating oxynitride layer over said first metallization structure and over said dielectric layer;
- a second metallization structure on and in physical contact with a top surface of said insulating oxynitride layer, wherein said second metallization structure comprises a second adhesion layer on said insulating oxynitride layer, and a bulk metal layer over said second adhesion layer, wherein said second adhesion layer physically contacts said top surface of said insulating oxynitride layer, wherein said second adhesion layer is under said bulk metal layer, but is not at sidewalls of said bulk metal layer, wherein said bulk metal layer has a thickness greater than 3 micrometers;
- a separating layer on said second metallization structure and on and in physical contact with said top surface of said insulating oxynitride layer, wherein said separating layer physically contacts a top surface of said bulk metal layer and said sidewalls of said bulk metal layer, wherein said separating layer comprises an insulating nitride layer over said top surface of said bulk metal layer and over said top surface of said insulating oxynitride layer;
- and
- a polymer layer on said separating layer, wherein an opening through said polymer layer and said separating layer is over a contact point of said top surface of said bulk metal layer, and said contact point is at a bottom of said opening.
7 more elements
An integrated circuit chip comprising:
- a semiconductor substrate;
- multiple transistors in and on said semiconductor substrate;
- an insulating layer over said semiconductor substrate;
- a first metallization structure over said insulating layer, wherein said first metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said first metallization structure comprises a metal line comprising a copper portion, and said first metallization structure further comprises a first adhesion layer under said copper portion and at sidewalls of said metal line, wherein said metal line has a thickness less than 2 micrometers;
- a dielectric layer between said first and second metal layers;
- a first insulating nitride layer over said first metallization structure and over said dielectric layer;
- a second metallization structure on and in physical contact with a top surface of said first insulating nitride layer, wherein said second metallization structure comprises a second adhesion layer on said first insulating nitride layer, and a bulk metal layer over said second adhesion layer, wherein said second adhesion layer physically contacts said top surface of said first insulating nitride layer, wherein said second adhesion layer is under said bulk metal layer, but is not at sidewalls of said bulk metal layer, wherein said bulk metal layer has a thickness greater than 3 micrometers;
- a separating layer on said second metallization structure and on and in physical contact with said top surface of said first insulating nitride layer, wherein said separating layer physically contacts a top surface of said bulk metal layer and said sidewalls of said bulk metal layer, wherein said separating layer comprises a second insulating nitride layer over said top surface of said bulk metal layer and over said top surface of said first insulating nitride layer;
- and
- a polymer layer on said separating layer, wherein an opening through said polymer layer and said separating layer is over a contact point of said top surface of said bulk metal layer, and said contact point is at a bottom of said opening.
7 more elements
An integrated circuit chip comprising:
- a semiconductor substrate;
- multiple transistors in and on said semiconductor substrate;
- an insulating layer over said semiconductor substrate;
- a metallization structure over said insulating layer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises a metal line comprising a copper portion, and said metallization structure further comprises a first adhesion layer under said copper portion and at sidewalls of said metal line, wherein said metal line has a thickness less than 2 micrometers;
- a dielectric layer between said first and second metal layers;
- a first insulating nitride layer over said metallization structure and over said dielectric layer;
- a first metal interconnect on and in physical contact with a top surface of said first insulating nitride layer, wherein said first metal interconnect is connected to said metallization structure through a first opening in said first insulating nitride layer;
- a second metal interconnect on and in physical contact with said top surface of said first insulating nitride layer, wherein said second metal interconnect comprises a second adhesion layer on said top surface of said first insulating nitride layer, and an electroplated copper layer over said second adhesion layer, wherein said second adhesion layer physically contacts said top surface of said first insulating nitride layer, wherein said second adhesion layer is under said electroplated copper layer, but is not at sidewalls of said electroplated copper layer, wherein said electroplated copper layer has a thickness greater than 3 micrometers;
- a second insulating nitride layer over said first and second metal interconnects, over said top surface of said first insulating nitride layer and between said first and second metal interconnects;
- and
- a polymer layer on said second insulating nitride layer and between said first and second metal interconnects, wherein a second opening through said polymer layer and said second insulating nitride layer is over a contact point of said electroplated copper layer of said second metal interconnect, and said contact point is at a bottom of said second opening.
8 more elements
An integrated circuit chip comprising:
- a semiconductor substrate;
- multiple transistors in and on said semiconductor substrate;
- a metallization structure over said semiconductor substrate, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, wherein said metallization structure comprises a metal line comprising a copper portion, and said metallization structure further comprises a first adhesion layer under said copper portion and at sidewalls of said metal line, wherein said metal line has a thickness less than 2 micrometers;
- a dielectric layer between said first and second metal layers;
- a first insulating layer over said metallization structure and over said dielectric layer;
- a first metal interconnect on and in physical contact with a top surface of said first insulating layer, wherein said first metal interconnect is connected to said metallization structure through a first opening in said first insulating layer;
- a second metal interconnect on and in physical contact with said top surface of said first insulating layer, wherein said second metal interconnect comprises a second adhesion layer on said top surface of said first insulating layer, and a third metal layer over said second adhesion layer, wherein said second adhesion layer physically contacts said top surface of said first insulating layer, wherein said second adhesion layer is under said third metal layer, but is not at sidewalls of said third metal layer;
- a second insulating layer over said first and second metal interconnects, over said top surface of said first insulating layer and between said first and second metal interconnects, wherein said second insulating layer comprises a nitride layer, wherein a second opening in said second insulating layer is over a contact point of said third metal layer of said second metal interconnect;
- and
- a polymer layer on said second insulating layer and between said first and second metal interconnects, wherein a third opening in said polymer layer is over said contact point.
7 more elements
Dependencies are inferred from the claim text.