Adhesive/spacer island structure for stacking over wire bonded die

A stacked semiconductor assembly comprising:

• a first semiconductor device having a first surface bounded by a periphery and having bond pads at the first surface;
• wires bonded to and extending from the bond pads outwardly past the periphery, the wires extending to a maximum height h above the first device;
• a package, comprising a package die mounted to and electrically interconnected with a package substrate, the package having an electrically non-conductive second surface positioned opposite the first surface, the package comprising a dielectric layer entirely covering the second surface of the package;
• the first device and the package defining a first region therebetween;
• an adhesive/spacer structure within the first region, the adhesive/spacer structure contacting the first and second surfaces and adhering the first device and the package to one another at a chosen separation, the adhesive/spacer structure comprising deformable spacer elements within an adhesive, and a material encapsulating the stacked assembly, the encapsulating material occupying the first region.

A multiple-die semiconductor chip package comprising:

• a substrate;
• a first die mounted to the substrate, the first die having a first surface bounded by a periphery and having bond pads at the first surface;
• wires bonded to and extending from the bond pads outwardly past the periphery to the substrate;
• a second die with an electrically non-conductive second surface positioned opposite the first surface and defining a die bonding region therebetween, the second surface of the second die comprising a dielectric layer entirely covering the second surface;
• adhesive/spacer structure within the die bonding region securing the first and second surfaces to one another at a chosen separation to create a multiple-die assembly;
• the adhesive/spacer structure comprising deformable spacer elements within an adhesive;
• the adhesive/spacer structure occupying a first percentage of the die bonding region, the first percentage being at most about 50%;
• and
• a material encapsulating the multiple-die assembly to create a multiple-die semiconductor chip package, the encapsulating material occupying a second percentage of the die bonding region.