Semiconductor structures and devices and methods of forming the same

#Embodiments of the present disclosure relate to semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material for use in memory devices and to methods of forming such semiconductor structures and devices including such structures.

#The continual demand for enhanced integrated circuit performance has resulted in, among other things, a dramatic reduction of semiconductor device geometries, and continual efforts to optimize the performance of structures within a semiconductor device. A number of improvements and innovations in fabrication processes, material composition, and layout of the active circuit levels of semiconductor devices have resulted in very high-density circuit designs. Increasingly, dense circuit design has not only improved a number of performance characteristics, it has also magnified the importance of semiconductor material properties and behaviors.

#In the past, most semiconductor devices were fabricated directly on a bulk silicon substrate. Recently, however, semiconductor manufacturers have started to fabricate semiconductor devices on substrates having varied compositions. One variety of substrate that is gaining in acceptance and popularity is silicon-on-insulator (SOI). The insulator configuration of SOI substrates offers semiconductor device designers a number of performance improvements over plain silicon substrates, such as improved leakage currents and improved latch-up characteristics. SOI substrates generally include a relatively thin silicon material disposed over an insulator, such as an oxide, which is, in turn, disposed over a bulk silicon material. SOI substrates are manufactured in a variety of ways. For example, an oxide may be foamed between bulk silicon substrates using conventional wafer bonding and layer transfer techniques and, thereafter, a portion of one of the bulk silicon substrates may be removed, for example, by abrasive planarization, to form a thin silicon film. Removal of the portion of the bulk silicon substrate may be inefficient and expensive due to the quantity of slurry and other consumables, such as polishing pads required for an abrasive planarization process, such as chemical-mechanical planarization (CMP). In addition, conventional planarization procedures may remove an undesirably large amount of the silicon material from the transfer wafer, reducing the number of times the transfer substrate may be used. In addition, an amount of the silicon material transferred from the bulk wafer that ends up in the SOI substrate, which is referred to herein as “transfer yield,” may be relatively low as a result of the need for subsequent removal of a substantial portion of the transferred silicon material.

#FIGS. 1A through 9E illustrate an embodiment of a method for forming a semiconductor structure according to the present disclosure;

#FIGS. 10A through 10E illustrate another embodiment of a method for forming a semiconductor structure according to the present disclosure; and

#FIGS. 11 illustrates an embodiment of a semiconductor device including a semiconductor structure such those formed according to the methods described with respect to FIGS. 1A through 10E.

#Methods of forming semiconductor structures are disclosed, as are semiconductor structures that include a conductive material underlying bodies of a semiconductor material. As used herein, the term “body” means and includes a volume of a semiconductor material. The bodies may be formed having a plurality of rails of a dielectric material between which the bodies of the semiconductor material are suspended. As used herein, the term “rails” means and includes a body of material having a substantially elongated shape, which may be used as a support for the bodies of semiconductor material. The conductive material, such as a metal, may be used as an interconnect structure to electrically couple components of memory devices. By way of example and not limitation, the conductive material may be used as a conductive line to electrically interconnect diode structures of a phase-change memory (PCRAM) device. As another example, the conductive material may be used as a buried strap to electrically interconnect memory cells, such as thyristors, and access devices, such as transistors. For example, the conductive material may be used to electrically interconnect thyristors and transistors of a thyristor random access memory (TRAM) device. The semiconductor structures provide metal interconnects for forming memory devices while reducing transfer yield and defectivity issues associated with conventional silicon-on-insulator (SOI) substrates.

#The following description provides specific details, such as material types and processing conditions in order to provide a thorough description of embodiments of the present disclosure. However, a person of ordinary skill in the art will understand that the embodiments of the present disclosure may be practiced without employing these specific details. Indeed, the embodiments of the present disclosure may be practiced in conjunction with conventional semiconductor fabrication techniques employed in the industry. In addition, the description provided below does not form a complete process flow for manufacturing a semiconductor device. Also, the semiconductor structures described below do not form a complete semiconductor device. Only those process acts and structures necessary to understand the embodiments of the present disclosure are described in detail below. Additional acts to form a complete semiconductor device from the semiconductor structures may be performed by conventional fabrication techniques.

#In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the present disclosure may be practiced. These embodiments are described in sufficient detail to enable a person of ordinary skill in the art to practice the present disclosure. However, other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of the invention. The illustrations presented herein are not meant to be actual views of any particular system, logic device, semiconductor device or memory cell, but are merely idealized representations that are employed to describe the embodiments of the present disclosure. The drawings presented herein are not necessarily drawn to scale. Additionally, elements common between drawings may retain the same numerical designation.