US 8,552,522 B2Granted

Dishing-free gap-filling with multiple CMPs

AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.

InventorsMing-Yuan Wu, Kong-Beng Thei, Chiung-Han Yeh, Harry Chuang, Mong-Song Liang

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Abstract

A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming patterned features over the semiconductor substrate, wherein gaps are formed between the patterned features; filling the gaps with a first filling material, wherein the first filling material has a first top surface higher than top surfaces of the patterned features; and performing a first planarization to lower the top surface of the first filling material, until the top surfaces of the patterned features are exposed. The method further includes depositing a second filling material, wherein the second filling material has a second top surface higher than the top surfaces of the patterned features; and performing a second planarization to lower the top surface of the second filling material, until the top surfaces of the patterned features are exposed.

Claims6

Dependent claims

A circuit structure comprising:

a semiconductor substrate;
a first and a second conductive gate strips over the semiconductor substrate, wherein the first and the second conductive gate strips have a gap therebetween, and wherein the first and the second conductive gate strips comprise first top surfaces;
a first inter-layer dielectric (ILD) in a gap between the first and the second conductive gate strips, wherein the first ILD comprises a second top surface lower than the first top surfaces, and wherein the second top surface is curved, with a center portion of the second top surface being lower than edge portions of the second top surface;
and
a second ILD over the first ILD, wherein the second ILD comprises a bottom surface contacting the second top surface, and a third top surface substantially coplanar with the first top surfaces, and wherein the second top surface and the bottom surface of the second ILD form a noticeable interface.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/151,666Filed 2 Jun 2011 · continuation
Priority: 14 May 2008
Published: US 2011/0227189 A122 Sep 2011
Granted: 8 Oct 2013
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H10W 20/056
Of conductive parts of the interconnections: by filling conductive material into holes, grooves or trenches
H10W 10/0143
Using trench refilling with dielectric materials, e.g. shallow trench isolations: comprising concurrently refilling multiple trenches having…
H10W 10/17
Isolation regions comprising dielectric materials: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
H10W 20/062
Of conductive parts of the interconnections: by smoothing of conductive parts, e.g. by planarisation

Family

Application12/152,380Parent of this continuation · filed 14 May 2008
US 2011/0227189 A1Pre-grant publication · published 22 Sep 2011
US 7,955,964 B2Parent of this continuation
US 2009/0286384 A1Published application
US 8,552,522 B2This patent

From the US filing history. Foreign family members aren’t listed.