Method for fabricating a damascene self-aligned ferroelectric random access memory (F-RAM) device structure employing reduced processing steps

A method for forming a ferroelectric device on a planar surface of a semiconductor substrate comprising:

• forming a relatively thick oxide layer on said planar surface;
• selectively etching an opening through said oxide layer in a pattern established by a non-erodible mask;
• applying and selectively etching a first aluminum oxide conformal layer to form first spacers on sidewalls of said opening;
• depositing a titanium aluminum nitride layer in a lower portion of said opening and separated from said first spacers;
• forming a bottom electrode of a ferroelectric capacitor over said first aluminum oxide conformal layer and in contact with said spacers laterally of said first aluminum oxide conformal layer;
• depositing, planarizing and selectively removing an oxide material to form an additional oxide layer adjoining said first spacers in said opening;
• depositing and selectively etching a second aluminum oxide layer to form second spacers on said additional oxide layer;
• depositing and etching a ferroelectric layer on said bottom electrode between said second spacers;
• forming a top electrode on said ferroelectric layer;
• forming a Ti/TiN and W contact to said bottom electrode through said oxide material;
• and
• also substantially concurrently forming a Ti/TiN and W contact to said top electrode.

A method for forming an integrated circuit device on a substrate including at least one contact stud, said method comprising:

• forming a first insulating layer on said substrate;
• removing a portion of said first insulating layer to produce an opening to an exposed surface of said substrate therein;
• forming first spacers on sidewalls of said opening;
• forming a first conductive layer in contact with said at least one contact stud on said exposed surface of said substrate separated from said first spacers on said sidewalls of said opening by a gap therebetween;
• forming a bottom electrode of a ferroelectric capacitor over said first conductive layer and in said gap laterally of said first conductive layer;
• forming a second insulating layer adjoining said spacers in said opening;
• forming second spacers on said second insulating layer in said opening;
• forming a ferroelectric dielectric on said bottom electrode between said second spacers;
• forming a top electrode on said ferroelectric dielectric;
• and
• forming an electrical contact to said top electrode.