Semiconductor device and manufacturing method thereof
AssigneeFujitsu Semiconductor Limited
InventorMasashi Shima
Life of this patent
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Abstract
A semiconductor device including a low-concentration impurity region formed on the drain side of an n-type MIS transistor, in a non-self-aligned manner with respect to an end portion of the gate electrode. A high-concentration impurity region is placed with a specific offset from the gate electrode and a sidewall insulating film. The semiconductor device enables the drain breakdown voltage to be sufficient and the on-resistance to decrease. A silicide layer is also formed on the surface of the gate electrode, thereby achieving gate resistance reduction and high frequency characteristics improvement.
Claims5
A semiconductor device comprising:
- a substrate;
- a gate electrode formed above the substrate with a first insulating film therebetween;
- a second insulating film formed on a sidewall of the gate electrode;
- a first region including first impurities of a first conductivity type formed in the substrate, overlapping with an end portion of the gate electrode;
- a second region including second impurities of the first conductivity type formed across the gate electrode opposite the first region in the substrate;
- a third region including third impurities of the first conductivity type formed next to the first region and away from the second insulating film in the substrate, having a third concentration of the third impurities higher than a first concentration of the first impurities of the first region;
- a fourth region including fourth impurities of the first conductivity type formed next to the second region in the substrate, having a fourth concentration of the fourth impurities higher than a second concentration of the second impurities of the second region;
- a fifth region including fifth impurities of a second conductivity type formed between the first region and second region in the substrate, a concentration of the fifth impurities of the second conductivity type being lower near the first region than near the second region within an area below the gate electrode between the first region and the second region;
- a third insulating film formed directly on the first region, being separated from the second insulating film;
- a first silicide layer formed directly on a surface of the first region between the second insulating film and the third insulating film and being in contact with a first part of the substrate, the first part having a first impurity concentration of the first conductivity type;
- a second silicide layer formed above a surface of the gate electrode;
- a third silicide layer formed directly on a surface of the third region and separated from the first silicide layer and being in contact with a second part of the substrate, the second part having a second impurity concentration of the first conductivity type higher than the first impurity concentration of the first conductivity type;
- and
- a fourth silicide layer formed above a surface of the fourth region.
Dependencies are inferred from the claim text.