Semiconductor device having ring-shaped gate electrode, design apparatus, and program

A semiconductor device comprising a comparison circuit that compares a voltage to be compared and a reference voltage, and outputs a comparison result signal having a voltage corresponding to the result of comparison, wherein

• the comparison circuit including:
• first and second transistors that are connected in parallel between a power supply wiring and a ground wiring,
• a third transistor that is connected between the first transistor and the power supply wiring, and
• a fourth transistor that is connected between the second transistor and the power supply wiring, wherein
• a gate of the third transistor, a gate of the fourth transistor, and a connection point between the first transistor and the third transistor are connected to one another,
• the reference voltage is supplied to either one of gates of the first and second transistors,
• the voltage to be compared is supplied to other of the gates of the first and second transistors,
• the comparison result signal is output from a connection point between the second transistor and the fourth transistor,
• the first to fourth transistors have respective ring-shaped first to fourth gate electrodes, wherein
• the semiconductor device further comprises:
• a plurality of external dummy electrodes that are arranged outside the first to fourth gate electrodes;
• and
• first to fourth internal dummy electrodes that are arranged inside the first to fourth gate electrodes, respectively, and wherein
• the first to fourth gate electrodes, the plurality of external dummy electrodes, and the first to fourth internal dummy electrodes are formed in the same layer.

A semiconductor device comprising:

• a substrate;
• first to fifth transistors that each includes a ring-shaped gate electrode formed on the substrate, a gate insulating film formed between the gate electrode and the substrate, a first diffusion region formed in the substrate corresponding to outside the gate electrode, and a second diffusion region formed in the substrate corresponding to inside the gate electrode;
• a first internal dummy electrode that is arranged inside and is formed in a same layer as the gate electrodes of the first transistor;
• a second internal dummy electrode that is arranged inside and is formed in the same layer as the gate electrode of the second transistor;
• a third internal dummy electrode that is arranged inside and is formed in the same layer as the gate electrode of the third transistor;
• a fourth internal dummy electrode that is arranged inside and is formed in the same layer as the gate electrode of the fourth transistor;
• a fifth internal dummy electrode that is arranged inside and is formed in the same layer as the gate electrode of the fifth transistor;
• first element isolation region that is embedded in the substrate corresponding to inside the gate electrodes of the first transistor;
• second element isolation region that is embedded in the substrate corresponding to inside the gate electrodes of the second transistor;
• substrate potential wiring that supplies a substrate potential;
• and
• a contact conductor that connects the substrate potential wiring and the substrate, wherein
• the first internal dummy electrode is formed on the first element isolation region,
• the second element isolation region has an opening,
• the contact conductor connecting the substrate potential wiring and the substrate through the opening,
• no element isolation region being formed in a region corresponding to inside the gate electrode of the third transistor,
• a plurality of the fourth internal dummy electrodes is provided,
• the fifth internal dummy electrode having a ring shape.