Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature and electrical connection of transistor gates through linear interconnect conductors in single interconnect layer

A method for creating a layout of an integrated circuit, comprising:

• operating a computer to define a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a line end spacing and a second end located adjacent to another line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
• wherein the gate electrode level region includes a first gate level feature that includes a first part that forms a gate electrode of a first transistor of a first transistor type and a second part that forms a gate electrode of a first transistor of a second transistor type, wherein the gate electrode of the first transistor of the first transistor type is substantially co-aligned with the gate electrode of the first transistor of the second transistor type along a first common line of extent in the first direction, and wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type through the first gate level feature,
• wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type,
• wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type,
• wherein the second and third gate level features are located in different gate level feature layout channels,
• wherein the first and second transistors of the first transistor type are collectively separated from the first and second transistors of the second transistor type by an inner portion of the gate electrode level region,
• wherein each of the first and second transistors of the first transistor type is formed in part by a shared diffusion region of a first diffusion type located on a first side of the first gate level feature,
• wherein each of the first and second transistors of the second transistor type is formed in part by a shared diffusion region of a second diffusion type located on a second side of the first gate level feature,
• wherein each of the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type is electrically connected to a common node, and
• wherein the first and second sides of the first gate level feature are opposite sides of the first gate level feature;
• operating a computer to define a plurality of interconnect level regions formed above the gate electrode level region;
• and
• operating a computer to define a first electrical connection to electrically connect the second gate level feature to the third gate level feature, the first electrical connection including a number of interconnect conductors located within one or more interconnect level regions of the plurality of interconnect level regions, wherein each of the number of interconnect conductors of the first electrical connection is linear-shaped.

A data storage device having program instructions stored thereon for generating a layout of an integrated circuit, comprising:

• program instructions for defining a gate electrode level region having a number of adjacently positioned gate level feature layout channels, each gate level feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate level feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a line end spacing and a second end located adjacent to another line end spacing, each gate level feature forming an electrically conductive path extending between its first and second ends,
• wherein the gate electrode level region includes a first gate level feature that includes a first part that forms a gate electrode of a first transistor of a first transistor type and a second part that forms a gate electrode of a first transistor of a second transistor type, wherein the gate electrode of the first transistor of the first transistor type is substantially co-aligned with the gate electrode of the first transistor of the second transistor type along a first common line of extent in the first direction, and wherein the gate electrode of the first transistor of the first transistor type is electrically connected to the gate electrode of the first transistor of the second transistor type through the first gate level feature,
• wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type,
• wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type,
• wherein the second and third gate level features are located in different gate level feature layout channels,
• wherein the first and second transistors of the first transistor type are collectively separated from the first and second transistors of the second transistor type by an inner portion of the gate electrode level region,
• wherein each of the first and second transistors of the first transistor type is formed in part by a shared diffusion region of a first diffusion type located on a first side of the first gate level feature,
• wherein each of the first and second transistors of the second transistor type is formed in part by a shared diffusion region of a second diffusion type located on a second side of the first gate level feature,
• wherein each of the shared diffusion region of the first diffusion type and the shared diffusion region of the second diffusion type is electrically connected to a common node, and
• wherein the first and second sides of the first gate level feature are opposite sides of the first gate level feature;
• program instructions for defining a plurality of interconnect level regions formed above the gate electrode level region;
• and
• program instructions for defining a first electrical connection to electrically connect the second gate level feature to the third gate level feature, the first electrical connection including a number of interconnect conductors located within one or more interconnect level regions of the plurality of interconnect level regions, wherein each of the number of interconnect conductors of the first electrical connection is linear-shaped.