Structure for CMOS ETSOI with multiple threshold voltages and active well bias capability

#The exemplary embodiments of this invention relate generally to semiconductor devices and fabrication techniques and, more specifically, relate to the fabrication of semiconductor transistor devices, such as those used in static random access memory (SRAM) and associated logic circuitry, using an extremely thin silicon on insulator (ETSOI) substrate.

#In silicon on insulator (SOI) technology a thin silicon layer is formed over an insulating layer, such as silicon oxide, which in turn is formed over a substrate. This insulating layer is often referred to as a buried oxide (BOX) layer or simply as a BOX. For a single BOX SOI wafer the thin silicon layer is divided into active regions by shallow trench isolation (STI) which intersects the BOX and provides a total isolation for active device regions formed in the silicon layer. Sources and drains of field effect transistors (FETs) are formed, for example, by ion implantation of n-type and/or p-type dopant material into the thin silicon layer with a channel region between the source and drain using the gate pattern to self-define the channel region. Prior to the formation of sources and drains, gates are formed on top of the channel region, for example, by deposition of a gate dielectric and conductor on the top surface of the thin silicon, followed by photolithographic patterning and etching. So-called back gates can also be formed under the active region on a single BOX SOI wafer using the BOX layer as the back gate dielectric. The back gates can be defined by either p-type or n-type doping.

#Transistors having back gates typically use relatively thin silicon and BOX layers to enable fully depleted device operation with a threshold voltage which is responsive to the back gate. Such FETs built in thin SOI technology with back gates have significant advantages such as, for example, reduced short channel effects, less threshold variability due to body doping fluctuations, and an ability to use the back gate voltage to adjust the threshold.

#FIG. 1 is a cross-sectional enlarged view (not to scale) of a portion of an ETSOI wafer that includes n-wells and p-type back gates with shallow intra-well STI that provides electrical isolation between adjacent FETS of the same well, and deep inter-well STI that extend completely through the n-well regions and sufficiently deep into the substrate so as to electrically isolate the n-well regions from one another along nfet/pfet boundaries and also boundaries between like devices with different desired bias voltages.

#FIG. 2 shows in greater detail one of the FETS of FIG. 1 in cross-section (not to scale).

#FIGS. 3A-3H show an example of an integrated back gate doping and dual STI process flow.

#In general, it can be advantageous to use a different back gate doping type (p-type or n-type) to achieve a desired transistor threshold voltage. Basically two different doping types are used to achieve two different threshold voltages. Changing the back gate type from n-type to p-type results in a change of the work function of approximately one volt, and is electrically equivalent to changing the applied potential by that amount. The use of the different back gate doping can be simpler to implement than modifying the work function of the top gate, and can reduce the number of required masks. In addition, different back gates can be used for other functions.

#It can also be advantageous to apply different back gate biases to nfets and pfets so as to tune performance, compensate for process variations and to optimize for given front gate work functions.

#It can also be advantageous to apply the same back gate bias to all nfets and the same back gate bias to all pfets in a block of logic circuits so that logic blocks of different thresholds may be interchanged without disruption.