Dummy gate for a high voltage transistor device

A semiconductor device, comprising:

• a first doped well and a second doped well each formed in a substrate, one of the first and second doped wells being doped with a P-type dopant, and the other one of the first and second doped wells being doped with an N-type dopant;
• a device gate structure disposed partially over the first and second doped wells, the device gate structure including a polysilicon gate electrode, wherein an entire upper surface of the gate electrode is silicided;
• and
• a dummy gate structure disposed over the second doped well, the dummy gate structure being separated from the device gate structure by a gap, wherein a region of the second doped well underneath the gap has a silicided surface.

A method of fabricating a semiconductor device, comprising:

• forming first and second oppositely-doped wells in a substrate;
• forming a device gate and a dummy gate over the substrate, the device gate being formed over the first and second wells, the dummy gate being formed over the second well, the first and second wells being separated by a gap;
• forming a protective mask to cover the gap between the first and second wells;
• forming a source region and a drain region having the same doping polarity as the source region, the source region being formed in a portion of the first well not protected by the device gate, the drain region being formed in a portion of the second well not protected by the dummy gate and the protective mask;
• removing the protective mask;
• and
• forming silicide surfaces for the source region, the drain region, the device gate, the dummy gate, and a portion of the second well exposed by the gap.