Semiconductor devices including elevated source and drain regions

A semiconductor device comprising:

• a substrate having a cell region and a peripheral region where active patterns are formed, respectively, an interval between the active patterns in the cell region being narrower than that between the active patterns in the peripheral region;
• isolating layer patterns formed in the cell region and the peripheral region of the substrate to define the active patterns, the isolating layer patterns having upper surfaces higher than those of the active patterns;
• a spacer layer formed on the upper surfaces of the active patterns and sidewalls of the isolating layer patterns;
• a first gate structure formed on the active patterns in the cell region, the first gate structure having a lower portion in recesses that are formed at the active patterns;
• a second gate structure formed on the active patterns in the peripheral region, the second gate structure having a flat structure;
• epitaxial layers formed in the active patterns in the cell region and the peripheral region having the first gate structure, the second gate structure and the spacer;
• and
• a channel region and a well region in the active patterns,
• wherein the substrate comprises a cell region and a peripheral region and wherein and an interval between the active patterns in the cell region is narrower than that between the active patterns in the peripheral region.