Vertical channel memory devices with nonuniform gate electrodes

A memory device comprising:

• vertically-spaced insulation layers stacked on a substrate;
• vertical channel regions extending through the insulation layers and electrically connected to the substrate;
• gate electrodes disposed between adjacent ones of the insulation layers surrounding the vertical channel regions;
• and
• at least one data storage layer disposed between the gate electrodes and the vertical channel regions, wherein the gate electrodes have a greater thickness at a first location near sidewalls of the insulation layers than at a second location farther away from the sidewalls of the insulation layers.