Method for reducing stress in epitaxial growth
AssigneeToshiba Techno Center Inc.
InventorSteven D. Lester
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AssigneeToshiba Techno Center Inc.
InventorSteven D. Lester
Estimating the term…
A device and method for making the same are disclosed. The device includes a substrate having a first TEC, a stress relief layer overlying the substrate, and crystalline cap layer. The crystalline cap layer overlies the stress relief layer. The cap layer has a second TEC different from the first TEC. The stress relief layer includes an amorphous material that relieves stress between the crystalline substrate and the cap layer arising from differences in the first and second TECs at a growth temperature at which layers are grown epitaxially on the cap layer. The device can be used to construct various semiconductor devices including GaN LEDs that are fabricated on silicon or SiC wafers. The stress relief layer is generated by converting a layer of precursor material on the substrate after the cap layer has been grown to a stress-relief layer.
A method for fabricating a semiconductor device, said method comprising:
A method for fabricating a semiconductor device, comprising:
Dependencies are inferred from the claim text.