# US 8,544,020 B1 · Cooperative preemption > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,544,020 B1 - Document ID: US8544020B1 - Status: Granted - Kind: B1 - Application number: 11/228,034 - Filed: 2005-09-14 - Granted: 2013-09-24 - Earliest claimed: 2004-09-14 - Assignees: Azul Systems, Inc. - Applicants: Gil Tene; Michael A. Wolf; Scott Sellers; Jack H. Choquette - Inventors: Gil Tene; Michael A. Wolf; Scott Sellers; Jack H. Choquette - Web page: https://patentgrep.com/patent/US8544020B1 ## CPC - G06F 8/315: {Object-oriented languages} - G06F 9/3001: {Arithmetic instructions} - G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE} - G06F 9/3004: {to perform operations on memory} - G06F 9/30087: {Synchronisation or serialisation instructions} - G06F 9/345: of multiple operands or results {(addressing multiple banks G06F12/06)} - G06F 9/355: Indexed addressing - G06F 9/3834: {Maintaining memory consistency} - G06F 9/3842: {Speculative instruction execution} - G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating} - G06F 9/3863: {using multiple copies of the architectural state, e.g. shadow registers} - G06F 9/461: {Saving or restoring of program or task context} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Preempting the execution of a thread is disclosed. Preempting includes receiving an indication that a preemption of the thread is desired and context switching the thread out at a thread safe point in the event that a thread safe point is reached. ## Claims ### Claim 1 A method of preempting the execution of a thread, including: receiving at a processor a first indication that a preemption of a first thread is desired in order to execute a second thread; in response to receiving the first indication, waiting for the first thread to reach a thread safe point, the thread safe point being a point in code at which if the first thread were to stop at the thread safe point, an operation that a third thread may want to perform on the first thread can be performed, wherein the first thread, the second thread and the third thread are different threads; in the event that the first thread reaches a thread safe point, context switching the first thread out at the thread safe point and context switching the second thread in; in the event that the first thread has not reached a thread safe point and it is detected that a second indication has been received, in response to the detection, preemptively context switching the first thread out and context switching the second thread in; and in the case of a single processor system, in the event that a fourth thread requests that all other threads be at a safe point, and each of the other threads has already entered a thread safe point, begin executing the fourth thread immediately. ### Claim 2 (depends on 1) A method as recited in claim 1, wherein the second indication includes a timer interrupt. ### Claim 3 (depends on 1) A method as recited in claim 1, wherein the second indication includes the expiry of a quantum. ### Claim 4 (depends on 1) A method as recited in claim 1, wherein the second indication includes a request to interrupt the first thread. ### Claim 5 (depends on 1) A method as recited in claim 1, wherein an operating system receives the first indication. ### Claim 6 (depends on 1) A method as recited in claim 1, wherein the first indication includes an event. ### Claim 7 (depends on 1) A method as recited in claim 1, wherein the first indication includes an event, wherein the event includes a thread of higher priority becoming ready to run. ### Claim 8 (depends on 1) A method as recited in claim 1, wherein the first indication includes a timer interrupt. ### Claim 9 (depends on 1) A method as recited in claim 1, wherein the first indication includes the expiry of a quantum. ### Claim 10 (depends on 1) A method as recited in claim 1, wherein the first indication includes a request to preempt the first thread. ### Claim 11 (depends on 1) A method as recited in claim 1, wherein the first indication includes an interrupt sent by another processor. ### Claim 12 (depends on 1) A method as recited in claim 1, further including calling a thread exception. ### Claim 13 (depends on 1) A method as recited in claim 1, wherein context switching includes setting a flag to indicate that a context switch at a thread safe point is required. ### Claim 14 (depends on 1) A method as recited in claim 1, further including the first thread checking a flag for a third indication that a context switch at a thread safe point is required. ### Claim 15 (depends on 1) A method as recited in claim 1, wherein context switching includes arming a thread safe point interrupt. ### Claim 16 (depends on 1) A method as recited in claim 1, further including the first thread executing a safe point instruction that triggers an armed safe point interrupt. ### Claim 17 (depends on 1) A method as recited in claim 1, further including calling a thread exception to indicate that a safe point interrupt has been triggered. ### Claim 18 (depends on 1) A method as recited in claim 1, wherein the first thread receives a third indication that a safe point is reached via a thread exception. ### Claim 19 (depends on 1) A method as recited in claim 1, wherein context switching the first thread out includes the first thread calling a system call while at a safe point. ### Claim 20 (depends on 1) A method as recited in claim 1, wherein context switching the first thread out includes the first thread calling a system call while at a safe point if a third indication that a context switch at a safe point is required is received. ### Claim 21 (depends on 1) A method as recited in claim 1, wherein at least one of the first thread, the second thread, and the third thread is running on a virtual machine. ### Claim 22 (depends on 1) A method as recited in claim 1, further including performing garbage collection. ### Claim 23 (depends on 1) A method as recited in claim 1, further including performing a debugging break point. ### Claim 24 (depends on 1) A method as recited in claim 1, wherein lock ownership within a thread safe point is avoided. ### Claim 25 (depends on 1) A method as recited in claim 1, further including sending a third indication that a preemption of a plurality of threads is desired. ### Claim 26 (depends on 1) A method as recited in claim 1, wherein context switching includes context switching a plurality of threads. ### Claim 27 (depends on 1) A method as recited in claim 1, further including sending a third indication that each of a plurality of threads needs to be at a thread safe point, wherein sending the indication includes setting a flag. ### Claim 28 (depends on 1) A method as recited in claim 1, further including sending a third indication that each of a plurality of threads needs to be at a thread safe point, wherein sending the indication includes acquiring a lock. ### Claim 29 (depends on 1) A method as recited in claim 1, further including sending a third indication that each of a plurality of threads needs to be at a thread safe point, wherein sending the indication includes setting a flag per thread. ### Claim 30 (depends on 1) A method as recited in claim 1, further including sending a third indication that each of a plurality of threads needs to be at a thread safe point, wherein sending the indication includes acquiring a lock per thread. ### Claim 31 (depends on 1) A method as recited in claim 1, further including sending a third indication that a global safe point is desired. ### Claim 32 (depends on 31) A method as recited in claim 31, wherein the first indication includes an event, wherein the event includes a thread of higher priority becoming ready to run. ### Claim 33 (depends on 32) A method as recited in claim 32, wherein context switching the first thread out includes the first thread calling a system call while at a safe point. ### Claim 34 (depends on 33) A method as recited in claim 33, wherein sending the third indication includes acquiring a lock. ### Claim 35 (depends on 31) A method as recited in claim 31, further including the first thread checking a flag for a fourth indication that a context switch at a thread safe point is required. ### Claim 36 (depends on 31) A method as recited in claim 31, further including the first thread executing a safe point instruction that triggers an armed safe point interrupt. ### Claim 37 A system for preempting the execution of a thread, including: a processor configured to: receive at a processor a first indication that a preemption of a first thread is desired in order to execute a second thread; in response to receiving the first indication, wait for the first thread to reach a thread safe point, the thread safe point being a point in code at which if the first thread were to stop at the thread safe point, an operation that a third thread may want to perform on the first thread can be performed, wherein the first thread, the second thread and the third thread are different threads; in the event that the first thread reaches a thread safe point, context switch the first thread out at the thread safe point and context switching the second thread in; in the event that the first thread has not reached a thread safe point and it is detected that a second indication has been received, in response to the detection, preemptively context switch the first thread out and context switch the second thread in; and in the case of a single processor system, in the event that a fourth thread requests that all other threads be at a safe point, and each of the other threads has already entered a thread safe point, begin executing the fourth thread immediately; and a memory coupled with the processor, wherein the memory provides the processor with instructions. ### Claim 38 A computer program product for preempting the execution of a thread, the computer program product being embodied in a non-transitory computer readable medium and comprising computer instructions for: receiving at a processor a first indication that a preemption of a first thread is desired in order to execute a second thread; in response to receiving the first indication, waiting for the first thread to reach a thread safe point, the thread safe point being a point in code at which if the first thread were to stop at the thread safe point, an operation that a third thread may want to perform on the first thread can be performed, wherein the first thread, the second thread and the third thread are different threads; in the event that the first thread reaches a thread safe point, context switching the first thread out at the thread safe point and context switching the second thread in; in the event that the first thread has not reached a thread safe point and it is detected that a second indication has been received, in response to the detection, preemptively context switching the first thread out and context switching the second thread in; and in the case of a single processor system, in the event that a fourth thread requests that all other threads be at a safe point, and each of the other threads has already entered a thread safe point, begin executing the fourth thread immediately.