# US 8,543,966 B2 · Test path selection and test program generation for performance testing integrated circuit chips

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- Number: US 8,543,966 B2
- Document ID: US8543966B2
- Status: Granted
- Kind: B2
- Application number: 13/294,210
- Filed: 2011-11-11
- Published: 2013-05-16
- Granted: 2013-09-24
- Earliest claimed: 2011-11-11
- Assignees: International Business Machines Corporation
- Applicants: Jeanne P. Bickford; Peter A. Habitz; Vikram Iyengar; David E. Lackey; Jinjun Xiong
- Inventors: Jeanne P. Bickford; Peter A. Habitz; Vikram Iyengar; David E. Lackey; Jinjun Xiong
- Web page: https://patentgrep.com/patent/US8543966B2

## CPC

- G01R 31/31726: {Synchronization, e.g. of test, clock or strobe signals; Signals in different clock domains; Generation of Vernier signals; Comparison and adjustment of the signals}
- G01R 31/318541: {Scan latches or cell details}
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)

## Abstract

A method of test path selection and test program generation for performance testing integrated circuits. The method includes identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains; selecting, from the data paths, critical paths for each clock domain of the multiple clock domains; using a computer, for each clock domain of the multiple clock domain, selecting the sensitizable paths of the critical paths; for each clock domain of the multiple clock domain, selecting test paths from the sensitizable critical paths; and using a computer, creating a test program to performance test the test paths.

## Claims

### Claim 1

A method, comprising:
identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains performing a beginning of life timing simulation for all data paths;
selecting, from said data paths, critical paths for each clock domain of the multiple clock domains, said critical paths being data paths between an input point and an output point wherein a time delay of a data signal presented at said input point and received at said output point must be between an upper performance specification and a lower performance specification;
using a computer, for each clock domain of said multiple clock domains, selecting the sensitizable paths of said critical paths;
for each clock domain of said multiple clock domain, selecting test paths from the sensitizable critical paths generating process parameter values for each critical path, said selecting said test paths from said sensitizable critical paths based in part on said process parameter values; and
using a computer, creating a test program to performance test said test paths.

### Claim 2 (depends on 1)

The method of claim 1, further including:
performing an AC noise simulation of said integrated circuit design and selecting a power level range having minimal signal-to-power noise coupling; and
performing said beginning of life timing simulation using said power level range.

### Claim 3 (depends on 1)

The method of claim 1, further including:
defining process parameters;
performing a beginning of life timing simulation for all data paths; and
generating process parameter values for each of said critical paths; and
selecting said test paths from said sensitizable critical paths such that sensitivity to said process parameters varies between said test paths.

### Claim 4 (depends on 1)

The method of claim 1, further including:
performing an AC noise simulation of said integrated circuit design; and
selecting said critical paths from low power supply voltage variation regions of said integrated circuit design.

### Claim 5 (depends on 1)

The method of claim 1, further including:
setting test program path delay limits for said test paths based on (i) a worst case of late data arrival and an early clock at an input point of a sensitizable path of said subsets of sensitizable paths and (ii) a best case of early data arrival and a late clock at an input point of said test paths.

### Claim 6 (depends on 1)

The method of claim 1, further including:
selecting said sensitizable paths of critical paths using an automatic test pattern generator check program.

### Claim 7 (depends on 1)

The method of claim 1, wherein all clocked elements of said critical paths are clocked with a same clock signal.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
for each clock domain:
selecting said sensitizable critical paths to include paths from different regions of said integrated circuit design and to include sensitizable paths of different Vt families;
generating timing test margins for each path of said sensitizable critical paths; and
setting up test clock frequencies for each path of said sensitizable critical paths.

### Claim 9 (depends on 1)

The method of claim 1, wherein said selecting said critical paths is performed using a branch-and-bound algorithm.

### Claim 10 (depends on 1)

The method of claim 1, further including:
performing an automatic test pattern generator check on said critical paths and retaining only critical paths that are sensitizable.

### Claim 11 (depends on 8)

The method of claim 8, wherein said test margins are based on the maximum frequency of the clock signal of said selected clock domain.

### Claim 12 (depends on 8)

The method of claim 8, further including:
creating a path file having an entry for each sensitizable critical path, each entry including physical path locations, designed path timing delay, designed slack and designed upper and lower timing bounds.

### Claim 13

A computer program product, comprising:
a computer usable storage device having a computer readable program code embodied therein, said computer readable program code comprising an algorithm adapted to implement a method for test path selection and test program generation for performance testing integrated circuit chips, said method comprising the steps of:
identifying clock domains having multiple data paths of an integrated circuit design having multiple clock domains performing a beginning of life timing simulation for all data paths;
selecting, from said data paths, critical paths for each clock domain of the multiple clock domains, said critical paths being data paths between an input point and an output point wherein a time delay of a data signal presented at said input point and received at said output point must be between an upper performance specification and a lower performance specification;
for each clock domain of said multiple clock domain, selecting the sensitizable paths of said critical paths;
for each clock domain of said multiple clock domain, selecting test paths from the sensitizable critical paths generating process parameter values for each critical path, said selecting said test paths from said sensitizable critical paths based in part on said process parameter values; and
creating a test program to performance test said test paths.

### Claim 14 (depends on 13)

The computer program product of claim 13, the method further including:
performing an AC noise simulation of said integrated circuit design and selecting a power level range having minimal signal-to-power noise coupling; and
performing said beginning of life timing simulation using said power level range.

### Claim 15 (depends on 13)

The computer program product of claim 13, the method further including:
defining process parameters;
performing a beginning of life timing simulation for all data paths; and
generating process parameter values for each of said critical paths; and
selecting said test paths from said sensitizable critical paths such that sensitivity to said process parameters varies between said test paths.

### Claim 16 (depends on 13)

The computer program product of claim 13, the method further including:
performing an AC noise simulation of said integrated circuit design; and
selecting said critical paths from low power supply voltage variation regions of said integrated circuit design.

### Claim 17 (depends on 13)

The computer program product of claim 13, the method further including:
setting test program path delay limits for said test paths based on (i) a worst case of late data arrival and an early clock at an input point of a sensitizable path of said subsets of sensitizable paths and (ii) a best case of early data arrival and a late clock at an input point of said test paths.

### Claim 18 (depends on 13)

The computer program product of claim 13, the method further including:
selecting said sensitizable paths of critical paths using an automatic test pattern generator check program.

### Claim 19 (depends on 13)

The computer program product of claim 13, wherein all clocked elements of said critical paths are clocked with a same clock signal.

### Claim 20 (depends on 13)

The computer program product of claim 13, the method further comprising:
for each clock domain:
selecting said sensitizable critical paths to include paths from different regions of said integrated circuit design and to include sensitizable paths of different Vt families;
generating timing test margins for each path of said sensitizable critical paths; and
setting up test clock frequencies for each path of said sensitizable critical paths.

### Claim 21 (depends on 13)

The computer program product of claim 13, wherein said selecting said critical paths is performed using a branch-and-bound algorithm.

### Claim 22 (depends on 13)

The computer program product of claim 13, the method further including:
performing an automatic test pattern generator check on said critical paths and retaining only critical paths that are sensitizable.

### Claim 23 (depends on 20)

The computer program product of claim 20, wherein said test margins are based on the maximum frequency of the clock signal of said selected clock domain.

### Claim 24 (depends on 20)

The computer program product of claim 20, the method further including:
creating a path file having an entry for each sensitizable critical path, each entry including physical path locations, designed path timing delay, designed slack and designed upper and lower timing bounds.