# US 8,543,965 B1 · Methods, systems, and articles of manufacture for smart pattern capturing and layout fixing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,965 B1 - Document ID: US8543965B1 - Status: Granted - Kind: B1 - Application number: 12/982,730 - Filed: 2010-12-30 - Granted: 2013-09-24 - Earliest claimed: 2010-06-12 - Assignees: Cadence Design Systems, Inc. - Applicants: Ya-Chieh Lai; Frank Gennari; Olivier Omedes; Olivier Pribetich - Inventors: Ya-Chieh Lai; Frank Gennari; Olivier Omedes; Olivier Pribetich - Web page: https://patentgrep.com/patent/US8543965B1 ## CPC - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Various embodiments are directed at methods and systems for implementing automatic fixing of a layout, implementing fuzzy pattern replacement, and implementing pattern capturing in a layout of an electronic circuit design. Various processes or modules comprise the act or module of identifying a first pattern from within an electronic circuit layout. The processes or modules also comprise identifying a fixing process or a replacement pattern for the first pattern and the act of performing pattern replacement or pattern fixing on the first pattern. The processes or modules may further comprise the act or module of searching the layout for patterns that match the first pattern, and the act or module of performing pattern replacement of pattern fixing on the patterns that match the first pattern. Some embodiments are also directed at articles of manufacture embodying a sequence of instructions for implementing the processes described here. ## Claims ### Claim 1 A computer implemented method for implementing automatic fixing of a layout of an electronic circuit design, the method comprising: using at least one processor that is configured or programmed for performing a process comprising: identifying a first pattern from within the layout; presenting approximate results of at least a fixing process of multiple candidate fixing processes for the first pattern; receiving, identifying, or creating the fixing process from the multiple candidate fixing processes for the first pattern by at least excluding a first area within the first pattern from consideration in receiving, identifying, or creating the fixing process for the first pattern; performing the fixing process on the first pattern; and associating the fixing process with the first pattern by at least embedding the fixing process or information about the fixing process into the first pattern so that the fixing process is identified when the first pattern is reused subsequently. ### Claim 2 (depends on 1) The computer implemented method of claim 1, the process further comprising: analyzing a result of the act of performing the fixing process within a context in which the first pattern is situated. ### Claim 3 (depends on 2) The computer implemented method of claim 2, in which the context comprises information or data about one or more geometries within a range of the first pattern in the electronic circuit design or an environment in which the first pattern is situated. ### Claim 4 (depends on 1) The computer implemented method of claim 1, the process further comprising: identifying one or more patterns that match the first pattern on one or more layers or purposes in the layout; and performing the fixing process on the one or more patterns that match the first pattern. ### Claim 5 (depends on 1) The computer implemented method of claim 1, the process further comprising: adjusting the first pattern after the fixing process is performed on the first pattern to improve the electronic circuit design. ### Claim 6 (depends on 1) The computer implemented method of claim 1, in which the fixing process comprises: performing a minimum perturbation fixing process, the minimum perturbation fixing process comprising: identifying or determining a central area within the first pattern; identifying one or more components within the central area; and modifying the one or more components within the central area to improve the electronic circuit design. ### Claim 7 (depends on 1) The computer implemented method of claim 1, the process further comprising: presenting a result of the fixing process for review or approval. ### Claim 8 (depends on 1) The computer implemented method of claim 1, the process further comprising: identifying one or more patterns that match the first pattern; and performing the fixing process on at least one of the one or more patterns. ### Claim 9 (depends on 1) The computer implemented method of claim 1, the process further comprising: identifying one or more patterns that do not match the first pattern; and performing the fixing process on at least one of the one or more patterns. ### Claim 10 (depends on 1) The computer implemented method of claim 1, the process further comprising: determining whether a result of the fixing process meets a requirement for performance, yield, manufacturability, functionality, correctness, or design intent of at least a part of the electronic circuit design. ### Claim 11 (depends on 1) The computer implemented method of claim 1, the process further comprising: integrating the fixing process into a user interface, in which the user interface also provides capability of editing a schematic representation or a physical representation of the electronic circuit design, implementing placement or routing of the electronic circuit, or implementing floorplanning for the electronic circuit design. ### Claim 12 (depends on 1) The computer implemented method of claim 1, the process further comprising: recommending the fixing process or another fixing process for the first pattern or for another pattern; and presenting a predicted result of the fixing process or another fixing process for the electronic circuit design. ### Claim 13 (depends on 1) The computer implemented method of claim 1, the process further comprising: storing information or data about the fixing process in one or more logs or macros. ### Claim 14 (depends on 13) The computer implemented method of claim 13, the process further comprising at least one of: undoing the fixing process or one or more first fixing processes to restore the electronic circuit design to one or more prior states by applying at least a first portion of the one or more logs or macros to the electronic circuit design; and redoing the fixing process or one or more second fixing processes to change a state of the electronic circuit design to one or more other states by applying at least a second portion of the one or more logs or macros to the electronic circuit design. ### Claim 15 A system for implementing automatic fixing of a layout of an electronic circuit design, comprising: at least one processor that is at least to: identify a first pattern from within the layout; present approximate results of at least a fixing process of multiple candidate fixing processes for the first pattern; receive, identify, or create the fixing process for the first pattern by at least excluding a first area within the first pattern from consideration in receiving, identifying, or creating the fixing process for the first pattern; perform the fixing process on the first pattern; and associate the fixing process with the first pattern by at least embedding the fixing process or information about the fixing process into the first pattern so that the fixing process is identified when the first pattern is reused subsequently. ### Claim 16 (depends on 15) The system of claim 15, wherein the at least one processor is further to: analyze a result of the act of performing the fixing process within a context in which the first pattern is situated, in which the context comprises information or data about one or more geometries within a range of the first pattern in the electronic circuit design or an environment in which the first pattern is situated. ### Claim 17 (depends on 15) The system of claim 15, wherein the at least one processor is further to: identify one or more patterns that match the first pattern on one or more layers or purposes in the layout; perform the fixing process on the one or more patterns that match the first pattern; adjust the first pattern after the fixing process is performed on the first pattern to improve the electronic circuit design; integrate the fixing process into a user interface, in which the user interface also provides capability of editing a schematic representation or a physical representation of the electronic circuit design, implementing placement or routing of the electronic circuit, or implementing floorplanning for the electronic circuit design; determine whether a result of the fixing process meets a requirement for performance, yield, manufacturability, functionality, correctness, or design intent of at least a part of the electronic circuit design; or perform a minimum perturbation fixing process, in which the at least one processor that is to perform the minimum perturbation fixing process is further to: identify or determine a central area within the first pattern; identify one or more components within the central area; and modify the one or more components within the central area to improve the electronic circuit design. ### Claim 18 (depends on 15) The system of claim 15, wherein the at least one processor is further to: recommend the fixing process or another fixing process for the first pattern or for another pattern; present a predicted result of the fixing process or another fixing process for the electronic circuit design; and store information or data about the fixing process in one or more logs or macros. ### Claim 19 (depends on 18) The system of claim 18, wherein the at least one processor is further to: undo the fixing process or one or more first fixing processes to restore the electronic circuit design to one or more prior states by applying at least a first portion of the one or more logs or macros to the electronic circuit design; or redo the fixing process or one or more second fixing processes to change a state of the electronic circuit design to one or more other states by applying at least a second portion of the one or more logs or macros to the electronic circuit design. ### Claim 20 An article of manufacture comprising a non-transitory computer readable storage medium having stored thereupon a sequence of instructions which, when executed by at least one processor, causes the processor to execute a method for implementing automatic fixing of a layout of an electronic circuit design, the method comprising: using the at least one processor that is configured or programmed for performing a process, the process comprising: identifying a first pattern from within the layout; presenting approximate results of at least a fixing process of multiple candidate fixing processes for the first pattern; receiving, identifying, or creating the fixing process for the first pattern by at least excluding a first area within the first pattern from consideration in receiving, identifying, or creating the fixing process for the first pattern; performing the fixing process on the first pattern; and associating the fixing process with the first pattern by at least embedding the fixing process or information about the fixing process into the first pattern so that the fixing process is identified when the first pattern is reused subsequently. ### Claim 21 (depends on 20) The article of manufacture of claim 20, the process further comprising: analyzing a result of the act of performing the fixing process within a context in which the first pattern is situated, in which the context comprises information or data about one or more geometries within a range of the first pattern in the electronic circuit design or an environment in which the first pattern is situated. ### Claim 22 (depends on 20) The article of manufacture of claim 20, the process further comprising at least one of: identifying one or more patterns that match the first pattern on one or more layers or purposes in the layout; performing the fixing process on the one or more patterns that match the first pattern; adjusting the first pattern after the fixing process is performed on the first pattern to improve the electronic circuit design; integrating the fixing process into a user interface, in which the user interface also provides capability of editing a schematic representation or a physical representation of the electronic circuit design, implementing placement or routing of the electronic circuit, or implementing floorplanning for the electronic circuit design; determining whether a result of the fixing process meets a requirement for performance, yield, manufacturability, functionality, correctness, or design intent of at least a part of the electronic circuit design; and performing a minimum perturbation fixing process, the minimum perturbation fixing process comprising: identifying or determining a central area within the first pattern; identifying one or more components within the central area; and modifying the one or more components within the central area to improve the electronic circuit design. ### Claim 23 (depends on 20) The article of manufacture of claim 20, the process further comprising: recommending the fixing process or another fixing process for the first pattern or for another pattern; presenting a predicted result of the fixing process or another fixing process for the electronic circuit design; and storing information or data about the fixing process in one or more logs or macros. ### Claim 24 (depends on 23) The article of manufacture of claim 23, the process further comprising at least one of: undoing the fixing process or one or more first fixing processes to restore the electronic circuit design to one or more prior states by applying at least a first portion of the one or more logs or macros to the electronic circuit design; and redoing the fixing process or one or more second fixing processes to change a state of the electronic circuit design to one or more other states by applying at least a second portion of the one or more logs or macros to the electronic circuit design.