# US 8,543,963 B2 · Global leakage power optimization

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- Number: US 8,543,963 B2
- Document ID: US8543963B2
- Status: Granted
- Kind: B2
- Application number: 12/695,545
- Filed: 2010-01-28
- Published: 2011-07-28
- Granted: 2013-09-24
- Earliest claimed: 2010-01-28
- Assignees: Synopsys, Inc.
- Applicants: Mahesh A. Iyer; Sudipto Kundu
- Inventors: Mahesh A. Iyer; Sudipto Kundu
- Web page: https://patentgrep.com/patent/US8543963B2

## CPC

- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 2119/06: Power analysis or power optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Some embodiments provide techniques and systems for optimizing a circuit design's global leakage power. During operation, the system can determine leakage potentials for logic gates in the circuit design, such that a logic gate's leakage potential indicates an amount or degree by which the logic gate's leakage power is decreasable. The system can then determine a processing order for processing the logic gates based at least on the leakage potentials. Next, the system can optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order.

## Claims

### Claim 1

A computer-executed method for optimizing a circuit design's leakage power, the method comprising:
determining leakage potentials for logic gates in the circuit design, wherein a logic gate's leakage potential is determined based on a difference between the logic gate's leakage power and a leakage power of another logic gate in a library;
determining a processing order for processing the logic gates based at least on the leakage potentials; and
optimizing, by computer, the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order, wherein said optimizing involves:
selecting a leakage-power-reducing transformation to apply to one or more logic gates, and
in response to determining that applying the selected leakage-power-reducing transformation to the one or more logic gates does not violate any design requirements in the circuit design, applying the selected leakage-power-reducing transformation to the one or more logic gates.

### Claim 2 (depends on 1)

The computer-executed method of claim 1, wherein determining the processing order includes ordering the logic gates based at least on a decreasing order of the leakage potentials.

### Claim 3 (depends on 2)

The computer-executed method of claim 2, wherein determining the processing order further includes:
associating a level with each logic gate so that each logic gate's level is greater than the highest level associated with logic gates that are electrically coupled to the logic gate's fan-in; and
ordering the logic gates in decreasing order of the associated levels.

### Claim 4 (depends on 1)

The computer-executed method of claim 1, wherein determining the processing order includes:
associating the logic gates with leakage potential bins, wherein each leakage potential bin is associated with a range of leakage potential values; and
ordering the logic gates based on the associated bins.

### Claim 5 (depends on 4)

The computer-executed method of claim 4, wherein the optimization process terminates if the decrease in the circuit design's leakage power is less than a predetermined threshold.

### Claim 6 (depends on 1)

The computer-executed method of claim 1, wherein optimizing the circuit design's leakage power by attempting to decrease the leakage power of logic gates includes:
determining a local context around one or more logic gates;
selecting a leakage-power-reducing transformation from a set of leakage-power-reducing transformations which do not violate any design requirements in the local context; and
in response to determining that the selected leakage-power-reducing transformation does not violate any design requirements in the circuit design, applying the selected leakage-power-reducing transformation to the one or more logic gates.

### Claim 7 (depends on 6)

The computer-executed method of claim 6, wherein the design requirements include one or more of: timing requirements, capacitance requirements, and transition requirements.

### Claim 8

A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for optimizing a circuit design's leakage power, the method comprising:
determining leakage potentials for logic gates in the circuit design, wherein a logic gate's leakage potential is determined based on a difference between the logic gate's leakage power and a leakage power of another logic gate in a library;
determining a processing order for processing the logic gates based at least on the leakage potentials; and
optimizing the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order, wherein said optimizing involves:
selecting a leakage-power-reducing transformation to apply to one or more logic gates, and
in response to determining that applying the selected leakage-power-reducing transformation to the one or more logic gates does not violate any design requirements in the circuit design, applying the selected leakage-power-reducing transformation to the one or more logic gates.

### Claim 9 (depends on 8)

The non-transitory computer-readable storage medium of claim 8, wherein determining the processing order includes ordering the logic gates based at least on a decreasing order of the leakage potentials.

### Claim 10 (depends on 9)

The non-transitory computer-readable storage medium of claim 9, wherein determining the processing order further includes:
associating a level with each logic gate so that each logic gate's level is greater than the highest level associated with logic gates that are electrically coupled to the logic gate's fan-in; and
ordering the logic gates in decreasing order of the associated levels.

### Claim 11 (depends on 8)

The non-transitory computer-readable storage medium of claim 8, wherein determining the processing order includes:
associating the logic gates with leakage potential bins, wherein each leakage potential bin is associated with a range of leakage potential values; and
ordering the logic gates based on the associated bins.

### Claim 12 (depends on 11)

The non-transitory computer-readable storage medium of claim 11, wherein the optimization process terminates if the decrease in the circuit design's leakage power is less than a predetermined threshold.

### Claim 13 (depends on 8)

The non-transitory computer-readable storage medium of claim 8, wherein optimizing the circuit design's leakage power by attempting to decrease the leakage power of logic gates includes:
determining a local context around one or more logic gates;
selecting a leakage-power-reducing transformation from a set of leakage-power-reducing transformations which do not violate any design requirements in the local context; and
in response to determining that the selected leakage-power-reducing transformation does not violate any design requirements in the circuit design, applying the selected leakage-power-reducing transformation to the one or more logic gates.

### Claim 14 (depends on 13)

The non-transitory computer-readable storage medium of claim 13, wherein the design requirements include one or more of: timing requirements, capacitance requirements, and transition requirements.

### Claim 15

An apparatus for optimizing a circuit design's leakage power, comprising:
a power-analysis mechanism configured to determine leakage potentials for logic gates in the circuit design, wherein a logic gate's leakage potential is determined based on the logic gate's leakage power and a leakage power of another logic gate in a library;
a sorting mechanism configured to determine a processing order for processing the logic gates based at least on the leakage potentials; and
a power-optimization mechanism configured to optimize the circuit design's leakage power by attempting to decrease leakage power of logic gates according to the processing order, wherein said optimizing involves:
selecting a leakage-power-reducing transformation to apply to one or more logic gates, and
in response to determining that applying the selected leakage-power-reducing transformation to the one or more logic gates does not violate any design requirements in the circuit design, applying the selected leakage-power-reducing transformation to the one or more logic gates.

### Claim 16 (depends on 15)

The apparatus of claim 15, wherein the sorting mechanism is further configured to order the logic gates based at least on a decreasing order of the leakage potentials.

### Claim 17 (depends on 16)

The apparatus of claim 16, wherein the sorting mechanism is further configured to:
associate a level with each logic gate so that each logic gate's level is greater than the highest level associated with logic gates that are electrically coupled to the logic gate's fan-in; and
order the logic gates in decreasing order of the associated levels.

### Claim 18 (depends on 15)

The apparatus of claim 15, wherein the sorting mechanism is further configured to:
associate the logic gates with leakage potential bins, wherein each leakage potential bin is associated with a range of leakage potential values; and
order the logic gates based on the associated bins.

### Claim 19 (depends on 18)

The apparatus of claim 18, wherein the power-optimization mechanism is configured to terminate the optimization process if the decrease in the circuit design's leakage power is less than a predetermined threshold.

### Claim 20 (depends on 15)

The apparatus of claim 15, wherein the power-optimization mechanism is further configured to:
determine a local context around one or more logic gates;
select a leakage-power-reducing transformation from a set of leakage-power-reducing transformations which do not violate any design requirements in the local context; and
in response to determining that the selected leakage-power-reducing transformation does not violate any design requirements in the circuit design, apply the selected leakage-power-reducing transformation to the one or more logic gates.

### Claim 21 (depends on 20)

The apparatus of claim 20, wherein the design requirements include one or more of: timing requirements, capacitance requirements, and transition requirements.