# US 8,543,956 B2 · Semiconductor integrated circuit and pattern layouting method for the same

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- Number: US 8,543,956 B2
- Document ID: US8543956B2
- Status: Granted
- Kind: B2
- Application number: 13/082,858
- Filed: 2011-04-08
- Published: 2011-10-13
- Granted: 2013-09-24
- Earliest claimed: 2010-04-13
- Assignees: Renesas Electronics Corporation
- Applicants: Kazuya Kamon
- Inventors: Kazuya Kamon
- Web page: https://patentgrep.com/patent/US8543956B2

## CPC

- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- H10D 89/00: Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10P 95/062: {involving a dielectric removal step}
- H10W 46/301: {for alignment}
- H10W 46/501: {for use before dicing}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional areas and a dummy pattern formed in a space area. The space area is positioned between predetermined functional areas. The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion.

## Claims

### Claim 1

A pattern lay-outing method for lay-outing patterns of a semiconductor integrated circuit comprising functional areas formed within a chip and including scribing areas, module areas and an I/O area; and a dummy pattern formed in a space area within the chip, the space area being defined between the functional areas, within any of the functional areas, and/or at a position spanning an area where any of the functional areas is formed and an area formed with none of the functional areas, the dummy pattern including: a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern; a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion; and a plurality of non-forming areas positioned on the inner periphery side of the first metal portion in an area where the second metal portion is not formed, the pattern lay-outing method comprising the steps of:
preparing reference plotting data defined by the functional areas formed within the chip;
oversizing the reference plotting data by a predetermined width;
subtracting the oversized reference plotting data from the chip to calculate the space area;
forming island areas within the space area, the island areas having a shape corresponding to the non-forming areas; and
subtracting the island areas from a space area positioned inside the outer edge of the dummy pattern to be formed.

### Claim 2 (depends on 1)

The pattern lay-outing method according to claim 1, wherein the non-forming areas have shapes comprising two or more kinds of shapes.

### Claim 3 (depends on 1)

The pattern lay-outing method according to claim 1, wherein
the non-forming areas are formed in a generally quadrangular shape and are disposed so as to be included within a plurality of predetermined areas respectively on the inner periphery side of the first metal portion,
the predetermined areas are a plurality of squares each having a one side length ratio satisfying Fibonacci sequence, the squares being arranged adjacently and spirally in order from shorter to longer one side length, and
the first metal portion, the second metal portion and the non-forming areas are configured so that the dummy pattern has self-analogy as a whole.

### Claim 4 (depends on 1)

The pattern lay-outing method according to claim 1, wherein
the non-forming areas are arranged in the shape of a fractal pattern, and
the first metal portion, the second metal portion and the non-forming areas are configured so that the dummy pattern has self-analogy as a whole.

### Claim 5 (depends on 1)

The pattern lay-outing method according to claim 1, wherein
the non-forming areas are each formed in a generally quadrangular shape and are arranged so as to include predetermined areas over a Penrose tile pattern defined on the inner periphery side of the first metal portion, and
the predetermined areas are arranged in five-time symmetry within the Penrose tile pattern.