# US 8,543,955 B1 · Apparatus and methods for time-multiplex field-programmable gate arrays

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- Number: US 8,543,955 B1
- Document ID: US8543955B1
- Status: Granted
- Kind: B1
- Application number: 12/716,999
- Filed: 2010-03-03
- Granted: 2013-09-24
- Earliest claimed: 2004-09-15
- Assignees: Altera Corporation
- Applicants: Sinan Kaptanoglu; David W. Mendel
- Inventors: Sinan Kaptanoglu; David W. Mendel
- Web page: https://patentgrep.com/patent/US8543955B1

## CPC

- H03K 19/17748: Structural details of configuration resources
- H03K 19/017581: {programmable}
- H03K 19/177: arranged in matrix form
- H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables
- H03K 19/1774: {for global signals, e.g. clock, reset}
- H03K 19/17796: for physical disposition of blocks
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A time-multiplexed field programmable gate array (TM-FPGA) includes programmable logic circuitry, programmable interconnect circuitry, and a plurality of context registers. A user's circuit can be mapped to the programmable logic circuitry, the programmable interconnect circuitry, and the plurality of context registers without the user's intervention in mapping the design.

## Claims

### Claim 1

A computer-implemented method of mapping an electronic circuit to resources in a time-multiplexed field programmable gate array (TM-FPGA), the method comprising:
obtaining a representation of the electronic circuit from a user;
using the computer to automatically partition the electronic circuit into a plurality of clusters; and
using the computer to automatically assign each cluster in the plurality of clusters to a context of the time-multiplexed field programmable gate array (TM-FPGA).

### Claim 2 (depends on 1)

The method according to claim 1, further comprising using the computer to automatically use a plurality of context registers to provide communication among a plurality of contexts of the time-multiplexed field programmable gate array (TM-FPGA).

### Claim 3 (depends on 2)

The method according to claim 2, further comprising using the computer to automatically optimize the number of context registers used.

### Claim 4 (depends on 3)

The method according to claim 3, further comprising using the computer to assign hardware resources to generate enable signals for the plurality of context registers.

### Claim 5 (depends on 2)

The method according to claim 2, wherein automatically using a plurality of context registers to provide communication among a plurality of contexts of the time-multiplexed field programmable gate array (TM-FPGA) further comprises using the computer to assign each context register in the plurality of context registers to a respective cycle of a clock signal.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the clock signal comprises an internal clock signal of the time-multiplexed field programmable gate array (TM-FPGA).

### Claim 7 (depends on 6)

The method according to claim 6, wherein the clock signal has a frequency equal to a frequency of a clock signal of the electronic circuit multiplied by the number of contexts in the plurality of contexts of the time-multiplexed field programmable gate array (TM-FPGA).

### Claim 8 (depends on 4)

The method according to claim 4, wherein the generated enable signals for the plurality of context registers correspond to respective cycles of the clock signal.

### Claim 9 (depends on 2)

The method according to claim 2, further comprising using the computer to determine whether the time-multiplexed field programmable gate array (TM-FPGA) includes a sufficient number of context registers to accommodate the electronic circuit.

### Claim 10 (depends on 3)

The method according to claim 3, wherein automatically optimizing the number of context registers used further comprises using the computer to minimize the number of context registers used.

### Claim 11

A computer-aided design (CAD) system for mapping an electronic circuit to resources in a time-multiplexed field programmable gate array (TM-FPGA), the CAD system comprising:
a computer, adapted to:
obtain a representation of the electronic circuit from a user;
partition automatically the electronic circuit into a plurality of clusters; and
assign automatically each cluster in the plurality of clusters to a context of the time-multiplexed field programmable gate array (TM-FPGA).

### Claim 12 (depends on 11)

The CAD system of claim 11, wherein the computer is further adapted to automatically use a plurality of context registers to provide communication among a plurality of contexts of the time-multiplexed field programmable gate array (TM-FPGA).

### Claim 13 (depends on 12)

The CAD system of claim 12, wherein the computer is further adapted to automatically optimize the number of context registers used.

### Claim 14 (depends on 13)

The CAD system of claim 13, wherein the computer is further adapted to assign hardware resources to generate enable signals for the plurality of context registers.

### Claim 15 (depends on 12)

The CAD system of claim 12, wherein to automatically use a plurality of context registers to provide communication among a plurality of contexts of the time-multiplexed field programmable gate array (TM-FPGA) the computer is further adapted to assign each context register in the plurality of context registers to a respective cycle of a clock signal.

### Claim 16 (depends on 15)

The CAD system of claim 15, wherein the clock signal comprises an internal clock signal of the time-multiplexed field programmable gate array (TM-FPGA).

### Claim 17

A non-transitory computer program product including computer-readable instructions, comprising:
a computer aided design (CAD) program adapted for processing by a computer to map an electronic circuit to resources in a time-multiplexed field programmable gate array (TM-FPGA), the CAD program adapted to cause the computer to:
obtain a representation of the electronic circuit from a user;
partition automatically the electronic circuit into a plurality of clusters; and
assign automatically each cluster in the plurality of clusters to a context of the time-multiplexed field programmable gate array (TM-FPGA).

### Claim 18 (depends on 17)

The non-transitory computer program product of claim 17, wherein the CAD program is further adapted to cause the computer to automatically use a plurality of context registers to provide communication among a plurality of contexts of the time-multiplexed field programmable gate array (TM-FPGA).

### Claim 19 (depends on 18)

The non-transitory computer program product of claim 18, wherein the CAD program is further adapted to cause the computer to automatically optimize the number of context registers used.

### Claim 20 (depends on 19)

The non-transitory computer program product of claim 19, wherein the CAD program is further adapted to cause the computer to assign hardware resources to generate enable signals for the plurality of context registers.