# US 8,543,951 B2 · Modeling approach for timing closure in hierarchical designs leveraging the separation of horizontal and vertical aspects of the design flow

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,543,951 B2
- Document ID: US8543951B2
- Status: Granted
- Kind: B2
- Application number: 13/649,909
- Filed: 2012-10-11
- Published: 2013-02-07
- Granted: 2013-09-24
- Earliest claimed: 2010-10-15
- Assignees: LSI Corporation
- Applicants: LSI Corporation
- Inventors: Vishwas M. Rao; Joseph J. Jamann; James C. Parker
- Web page: https://patentgrep.com/patent/US8543951B2

## CPC

- G06F 30/3312: Timing analysis
- G06F 2119/12: Timing analysis or timing optimisation
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method of designing a model of an integrated circuit block, an electronic design automation tool and a non-transitory computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating an input and output timing budget for the block based on design constraints of the block and a netlist of the block, (2) updating the input and output timing budget with clock customization data based on designer knowledge of the integrated circuit and (3) providing the model for the block based on the update of the input and output timing budget, wherein the model represents clock information of the block separately from data path information of the block.

## Claims

### Claim 1

A method of generating a model of a block of an integrated circuit, comprising:
generating, by a computer, an input and output timing budget for said block based on design constraints of said block and a netlist of said block;
updating said input and output timing budget with clock customization data based on designer knowledge of said integrated circuit; and
providing said model for said block based on said update of said input and output timing budget, wherein said model:
represents clock information of said block separately from data path information of said block;
includes external points for both input and output clock signals; and
includes internal points injected between inputs and outputs of said external points, wherein said internal points:
separate said clock information from said data information; and
include at least two of:
a delayed input clock;
an internal clock;
a generated clock;
a delayed internal clock; and
a delayed generated clock.

### Claim 2 (depends on 1)

The method as recited in claim 1 wherein said model includes interface timing information between said block and said integrated circuit based on said clock customization data.

### Claim 3 (depends on 2)

The method as recited in claim 2 wherein said interface timing information is a merger between said clock customization data and circuit timing information of said block.

### Claim 4 (depends on 1)

The method as recited in claim 1 wherein said external points represent interfaces between said block and said integrated circuit.

### Claim 5 (depends on 4)

The method as recited in claim 4 wherein said external points include a clock input and, separated therefrom, a data input associated with said clock input.

### Claim 6 (depends on 5)

The method as recited in claim 5 wherein said external points further include a data output for said data input, wherein said delayed input clock internal point is injected between said data input point and said data output point.

### Claim 7 (depends on 5)

The method as recited in claim 5 wherein said external points further include a generated data input and a generated data output, wherein said delayed generated clock internal point is injected therebetween.

### Claim 8 (depends on 7)

The method as recited in claim 7 wherein said external points further include a generated clock output, said generated data output and said generated clock output forming a synchronous interface for said block.

### Claim 9

An electronic design automation tool including a model generator embodied as a series of operating instructions stored on a non-transitory computer-readable medium that are executed by a processor, the model generator comprising:
a block analyzer configured to analyze design constraints and structures of a block of an integrated circuit to generate input and output timing constraints for said block; and
an interface timing generator configured to combine said input and output timing constraints with clock customization data based on designer knowledge of said integrated circuit to generate interface timing parameters for said block;
wherein the model generator provides a model of said block and wherein said model for said block includes:
external points for both input and output clock signals;
internal points injected between inputs and outputs of said external points, wherein said internal points:
separate clock information from data information; and
include at least two of:
a delayed input clock;
an internal clock;
a generated clock;
a delayed internal clock; and
a delayed generated clock.

### Claim 10 (depends on 9)

The electronic design automation tool as recited in claim 9 further comprising a translator configured to generate a model of said block based on said interface timing parameters.

### Claim 11 (depends on 9)

The electronic design automation tool as recited in claim 9 wherein an ideal clock and a propagated clock from a design flow of said integrated circuit are both represented in said model.

### Claim 12

A non-transitory computer-readable medium having stored thereon instructions that, when executed, direct the operation of a processor to implement a method for designing an integrated circuit, said method comprising:
generating an input and output timing budget for said block based on design constraints of said block and a netlist of said block;
updating said input and output timing budget with clock customization data based on designer knowledge of said integrated circuit; and
providing said model for said block based on said update of said input and output timing budget, wherein said model:
represents clock information separately from data path information;
includes external points for both input and output clock signals; and
includes internal points injected between inputs and outputs of said external points, wherein said internal points:
separate said clock information from said data information; and
include at least two of:
a delayed input clock;
an internal clock;
a generated clock;
a delayed clock; and
a delayed generated clock.

### Claim 13 (depends on 12)

The computer-readable medium as recited in claim 12 wherein said model includes interface timing information between said block and said integrated circuit based on said clock customization data.

### Claim 14 (depends on 13)

The computer-readable medium as recited in claim 13 wherein said interface timing information is a merger between said clock customization data and circuit timing information of said block.

### Claim 15 (depends on 13)

The computer-readable medium as recited in claim 13 wherein said external points represent interfaces between said block and said integrated circuit.

### Claim 16 (depends on 15)

The computer-readable medium as recited in claim 15 wherein said external points include a clock input and, separated therefrom, a data input associated with said clock input.

### Claim 17 (depends on 16)

The computer-readable medium as recited in claim 16 wherein said external points further include a data output for said data input, wherein said delayed input clock internal point is injected between said data input point and said data output point.

### Claim 18 (depends on 16)

The computer-readable medium as recited in claim 16 wherein said external points further include a generated data input and a generated data output, wherein said delayed generated clock internal point is injected therebetween.