# US 8,543,950 B2 · Computer-aided design system to automate scan synthesis at register-transfer level

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- Number: US 8,543,950 B2
- Document ID: US8543950B2
- Status: Granted
- Kind: B2
- Application number: 13/490,721
- Filed: 2012-06-07
- Published: 2012-09-27
- Granted: 2013-09-24
- Earliest claimed: 2001-03-30
- Assignees: Syntest Technologies, Inc.
- Applicants: Laung-Terng (L.-T.) Wang; Augusli Kifli; Fei-Sheng Hsu; Shih-Chia Kao; Xiaoqing Wen; Shyh-Horng Lin; Hsin-Po Wang
- Inventors: Laung-Terng (L.-T.) Wang; Augusli Kifli; Fei-Sheng Hsu; Shih-Chia Kao; Xiaoqing Wen; Shyh-Horng Lin; Hsin-Po Wang
- Web page: https://patentgrep.com/patent/US8543950B2

## CPC

- G01R 31/31704: {Design for test; Design verification (concerning scan tests G01R31/318583; computer-aided design G06F30/00)}
- G01R 31/318314: {Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages (simulation software G01R31/318357; emulators G06F11/261)}
- G01R 31/318364: {as a result of hardware simulation, e.g. in an HDL environment (computer-aided simulation of circuits G06F30/3308)}
- G01R 31/318583: {Design for test}
- G01R 31/318594: {Timing aspects (clock circuits G01R31/318552)}
- G06F 30/30: Circuit design
- G06F 30/323: Translation or migration, e.g. logic to logic, hardware description language [HDL] translation or netlist translation
- G06F 30/327: Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
- G06F 30/33: Design verification, e.g. functional simulation or model checking
- G06F 30/3308: using simulation
- G06F 30/331: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
- G06F 30/333: Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
- G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

## Claims

### Claim 1

A method of performing interactive scan repair using a computer for repairing broken scan cells within each broken scan chain in a scan-based integrated circuit modeled at RTL (register-transfer level), the integrated circuit having a plurality of clock domains and each domain having one scan clock; said method comprising using the computer to perform the steps of:
a. compiling scan-based HDL (hardware description language) code that represents said integrated circuit at RTL into a design database;
b. receiving scan constraints from an external source, said scan constraints further comprising selected broken control points to be repaired;
c. repairing said selected broken control points within each said broken scan chain according to said scan constraints; and
d. generating the scan-repaired HDL code at RTL.

### Claim 2 (depends on 1)

The method of claim 1, wherein said repairing said selected broken control points within each said broken scan chain further comprises interactively guiding designers to select said scan-repaired HDL code for repairing each said selected broken control point on said design database.

### Claim 3 (depends on 1)

The method of claim 1, wherein said repairing said selected broken control points within each said broken scan chain further comprises making a plurality of interactive repair suggestions and repairing each said selected broken control point according to a selected said repair suggestion.

### Claim 4 (depends on 1)

The method of claim 1, wherein said repairing said selected broken control points within each said broken scan chain further comprises interactively highlighting selected RTL codes and said selected broken control points which have been repaired on a schematic viewer, HDL code viewer, or a waveform viewer.