# US 8,543,893 B2 · Receiver for error-protected packet-based frame

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- Number: US 8,543,893 B2
- Document ID: US8543893B2
- Status: Granted
- Kind: B2
- Application number: 12/837,556
- Filed: 2010-07-16
- Published: 2011-03-03
- Granted: 2013-09-24
- Earliest claimed: 2009-09-02
- Assignees: Agere Systems Inc.
- Applicants: Atul Kisanrao Hedaoo; Rayesh Kashinath Raikar
- Inventors: Atul Kisanrao Hedaoo; Rayesh Kashinath Raikar
- Web page: https://patentgrep.com/patent/US8543893B2

## CPC

- H03M 13/05: using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits {(H03M13/2906 takes precedence)}
- H03M 13/13: Linear codes
- H04L 1/0052: {Realisations of complexity reduction techniques, e.g. pipelining or use of look-up tables}
- H04L 1/0057: {Block codes (H04L1/0061, H04L1/0064 take precedence)}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

In one embodiment, a receiver for a frame of media packets employing the real-time transmission protocol (RTP) and forward error correction (FEC) is disclosed. The receiver comprises a packet buffer and an FEC decoder. After a packet is received by the packet buffer, the FEC decoder reads the packet and, as part of FEC processing, performs an XOR operation on the packet, without waiting for the entire frame (or, indeed, for any subsequent packet of the frame) to be received. The XOR operation results are accumulated until sufficient packets are received to reconstruct a missing packet in the frame. Because the XOR operations are performed immediately after a packet is received, without any delay from waiting for subsequent packets, the receiver has a very low latency, and the packet buffer may be relatively small.

## Claims

### Claim 1

A method for performing error-correction (EC) processing in a receiver, the method comprising:
(a) a receiver serially receiving a subset of packets of a first frame comprising three or more data packets and an EC packet
(b) the receiver performing EC processing on the subset of packets of the first frame to reconstruct at least one packet of the first frame, wherein the EC processing is initiated before the entire subset of packets is received;
(c) serially receiving a subset of packets of a second frame comprising three or more data packets and an EC packet; and
(d) performing EC processing on the subset of packets of the second frame to reconstruct at least one packet of the second frame, wherein the EC processing of the second frame is initiated before completion of the EC processing of the first frame.

### Claim 2 (depends on 1)

The invention of claim 1, wherein the EC processing comprises processing each packet in the subset upon receipt without waiting to receive a subsequent packet in the subset.

### Claim 3 (depends on 2)

The invention of claim 2, wherein, for at least one received packet in the subset, the EC processing comprises:
(b1) performing a mathematical operation on the received packet and a value stored in a memory; and
(b2) storing a result of the mathematical operation as the value stored in the memory for a subsequent mathematical operation.

### Claim 4 (depends on 3)

The invention of claim 3, wherein, for the last received packet in the subset, the EC processing comprises:
(b3) performing a last mathematical operation on the last received packet and the value stored in the memory; and
(b4) reconstructing a missing data packet of the first frame based on a result of the last mathematical operation.

### Claim 5 (depends on 1)

The invention of claim 1, wherein the EC processing of the first frame is initiated before initiation of the EC processing of the second frame.

### Claim 6 (depends on 1)

The method of claim 1, further comprising:
(a1) storing, in a packet buffer, each packet in the subset of packets of the first frame;
(a2) reading each packet from the packet buffer before performing EC processing on the packet; and
(c) storing a reconstructed packet in the packet buffer, after EC processing on each packet in the subset of packets of the first frame is completed.

### Claim 7

A receiver comprising:
a packet buffer adapted to serially receive a subset of packets of a first frame comprising three or more data packets and an error-correction (EC) packet; and
an EC decoder adapted to perform EC processing on the subset of packets of the first frame to reconstruct at least one packet of the first frame, wherein the EC processing is initiated before the entire subset of packets is received.

### Claim 8 (depends on 7)

The invention of claim 7, wherein the EC decoder is adapted to perform EC processing on each packet in the subset upon receipt without waiting for the packet buffer to receive a subsequent packet in the subset.

### Claim 9 (depends on 8)

The invention of claim 8, wherein:
the receiver further comprises a memory; and
the EC decoder is adapted, for at least one received packet in the subset, to:
perform a mathematical operation on the received packet and a value stored in the memory; and
store a result of the mathematical operation as the value stored in the memory for a subsequent mathematical operation.

### Claim 10 (depends on 9)

The invention of claim 9, wherein, for the last received packet in the subset, the EC decoder is adapted to:
perform a last mathematical operation on the last received packet and the value stored in the memory; and
reconstruct a missing data packet of the first frame based on a result of the last mathematical operation.

### Claim 11 (depends on 7)

The invention of claim 7, wherein:
the packet buffer is adapted to serially receive a subset of packets of a second frame comprising three or more data packets and an EC packet; and
the EC decoder is adapted to:
perform EC processing on the subset of packets of the second frame to reconstruct at least one packet of the second frame, and
initiate the EC processing of the second frame before completing the EC processing of the first frame.

### Claim 12 (depends on 11)

The invention of claim 11, wherein the EC decoder is adapted to initiate the EC processing of the first frame before initiating the EC processing of the second frame.

### Claim 13 (depends on 7)

The invention of claim 7, wherein:
the packet buffer is adapted to store each packet in the subset of packets of the first frame;
the EC decoder is adapted to read each packet from the packet buffer before performing EC processing on the packet; and
the EC decoder is adapted to store a reconstructed packet in the packet buffer, after EC processing each packet in the subset of packets of the first frame.

### Claim 14

An apparatus for performing error-correction (EC) processing in a receiver, the apparatus comprising:
(a) means for serially receiving a subset of packets of a first frame comprising three or more data packets and an EC packet;
(b) means for performing EC processing on the subset of packets of the first frame to reconstruct at least one packet of the first frame, wherein the EC processing is initiated before the entire subset of packets is received;
(c) means for serially receiving a subset of packets of a second frame comprising three or more data packets and an EC packet; and
(d) means for performing EC processing on the subset of packets of the second frame to reconstruct at least one packet of the second frame, wherein the EC processing of the second frame is initiated before completion of the EC processing of the first frame.
