# US 8,543,892 B2 · Memory device and method of storing data with error correction using codewords > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,892 B2 - Document ID: US8543892B2 - Status: Granted - Kind: B2 - Application number: 13/625,554 - Filed: 2012-09-24 - Published: 2013-01-17 - Granted: 2013-09-24 - Earliest claimed: 2008-05-23 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Kwang Soo Seol; Sung-Il Park; Kyoung Lae Cho; In-Sung Joe - Web page: https://patentgrep.com/patent/US8543892B2 ## CPC - H03M 13/611: {Specific encoding aspects, e.g. encoding by means of decoding} - G06F 11/1072: {in multilevel memories} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/26: Sensing or reading circuits; Data output circuits - H03M 13/27: using interleaving techniques - H03M 13/2732: {Convolutional interleaver; Interleavers using shift-registers or delay lines like, e.g. Ramsey type interleaver} - H03M 13/2906: {using block codes (H03M13/2957 takes precedence)} - H03M 13/3707: {Adaptive decoding and hybrid decoding, e.g. decoding methods or techniques providing more than one decoding algorithm for one code} - H03M 13/3715: {Adaptation to the number of estimated errors or to the channel state} - H03M 13/47: Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37 - G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor} - G11C 29/00: Checking stores for correct operation {; Subsequent repair}; Testing stores during standby or offline operation - H03M 13/13: Linear codes - H03M 13/15: Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes (H03M13/17 takes precedence) - H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Memory devices and/or methods of storing memory data bits are provided. A memory device includes a multi-level cell (MLC) array including a plurality of MLCs, an error correction unit configured to encode data to be recorded in an MLC, where the encoded data is converted to convert the encoded data into a codeword, an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern included in the codeword and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern. According to the above memory devices and/or methods, it is possible to efficiently reduce a data error that occurs when the data is stored for a relatively long period of time, thereby improving reliability. ## Claims ### Claim 1 A memory device comprising: a multi-level cell (MLC) array including a plurality of MLCs; an error correction unit configured to encode data, where the encoded data is converted into a codeword; an error pattern analysis unit configured to analyze a first data pattern included in the codeword corresponding to an error pattern; and a data conversion unit configured to convert the analyzed first data pattern into a second data pattern, wherein the error pattern analysis unit controls the data conversion unit to convert the first data pattern into the second data pattern. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the second data pattern excludes the error pattern and corresponds to a data pattern having a low frequency of errors. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the data conversion unit performs interleaving of the first data pattern to convert the first data pattern into the second data pattern. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the MLC corresponds to a four-level cell and the data conversion unit transposes a Most Significant Bit (MSB) and a Least Significant Bit (LSB) of a data logical page corresponding to the first data pattern to generate the second data pattern. ### Claim 5 (depends on 1) The memory device of claim 1, wherein the data conversion unit performs a bit operation in a data logical page corresponding to the first data pattern to generate the second data pattern including the bit-operated data logical page. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the data conversion unit performs a data-shift operation in a data logical page corresponding to the first data pattern to generate the second data pattern including the shift-operated data logical page. ### Claim 7 (depends on 1) The memory device of claim 1, wherein, the error pattern analysis unit reads and extracts the codeword including the second data pattern recorded in the MLC to analyze the codeword, the data conversion unit converts the second data pattern into the first data pattern corresponding to the error pattern, and the error correction unit decodes the codeword including the first data pattern. ### Claim 8 (depends on 7) The memory device of claim 7, wherein the data conversion unit performs de-interleaving of the second data pattern to convert the de-interleaved second data pattern into the first data pattern. ### Claim 9 (depends on 7) The memory device of claim 7, wherein the data conversion unit performs an inverse bit operation in a data logical page corresponding to the second data pattern to generate the first data pattern including the inverse bit-operated data logical page. ### Claim 10 (depends on 7) The memory device of claim 7, wherein the data conversion unit inversely performs a data-shift operation in a data logical page corresponding to the second data pattern to generate the first data pattern including the inverse shift-operated data logical page. ### Claim 11 (depends on 7) The memory device of claim 7, wherein the error correction unit increases or decreases a read voltage applied to the MLC and analyzes a bit error based on the increase or decrease of the read voltage to select the codeword corresponding to the analyzed bit error based on the error pattern when the codeword is outside an error correcting capability range. ### Claim 12 (depends on 11) The memory device of claim 11, wherein the error correction unit selects the codeword in which a number of the error patterns is highest when an increase or decrease of a number of bit errors with respect to the bit error does not exist.