# US 8,543,888 B2 · Programmable cyclic redundancy check CRC unit

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- Number: US 8,543,888 B2
- Document ID: US8543888B2
- Status: Granted
- Kind: B2
- Application number: 12/776,476
- Filed: 2010-05-10
- Published: 2010-12-09
- Granted: 2013-09-24
- Earliest claimed: 2009-06-09
- Assignees: Microchip Technology Incorporated
- Applicants: Sudhir Bommena; Igor Wojewoda; Yong Yuenyongsgool; Vijay Dubey; Roshan Samuel; Jonathan Brant Ivey
- Inventors: Sudhir Bommena; Igor Wojewoda; Yong Yuenyongsgool; Vijay Dubey; Roshan Samuel; Jonathan Brant Ivey
- Web page: https://patentgrep.com/patent/US8543888B2

## CPC

- H03M 13/09: Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit
- H03M 13/6516: {Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields}
- H03M 13/6569: {Implementation on processors, e.g. DSPs, or software implementations}
- H03M: CODING; DECODING; CODE CONVERSION IN GENERAL (using fluidic means F15C4/00; optical analogue/digital converters G02F7/00; coding, decoding or code conversion, specially adapted for particular applications, see the relevant subclasses, e.g. G01D, G01R, G06F, G06T, G09G, G10L, G11B, G11C, H04B, H04L, H04M, H04N; ciphering or deciphering for cryptography or other purposes involving the need for secrecy G09C)

## Abstract

A cyclic redundancy check (CRC) unit has a programmable CRC engine, a variable buffer memory operable to store k words wherein each word has n-bits, wherein k and n can be varied, and shift logic operable to shift data from the variable buffer memory into the programmable CRC engine.

## Claims

### Claim 1

A cyclic redundancy check (CRC) unit, comprising:
a programmable CRC engine comprising a linear feedback shift register (LFSR);
a variable buffer memory operable to store k words wherein each word comprises n-bits, wherein k and n can be varied; and
a controllable shift buffer and a control register coupled with the controllable shift buffer for setting a shift direction operable to serially shift data from said variable buffer memory into the LFSR said programmable CRC engine using a left or right shift operation depending on a value stored in said control register.

### Claim 2 (depends on 1)

The CRC unit according to claim 1, wherein the variable buffer memory is a first-in first-out (FIFO) memory.

### Claim 3 (depends on 2)

The CRC unit according to claim 2, wherein each n-bit word in the variable buffer memory comprises m bytes, wherein m can vary from 1 to Q, Q being an integer greater 1.

### Claim 4 (depends on 3)

The CRC unit according to claim 3, wherein Q=4.

### Claim 5 (depends on 1)

The CRC unit according to claim 1, wherein the control register further controls parameters of said programmable CRC engine.

### Claim 6 (depends on 1)

The CRC unit according to claim 1, wherein the control register comprises a single bit indicating the shift direction.

### Claim 7 (depends on 6)

The CRC unit according to claim 6, wherein the variable buffer memory comprises a counter whose content indicates the number of available n-bit words.

### Claim 8 (depends on 7)

The CRC unit according to claim 7, wherein the counter generates an interrupt signal when it reaches a predetermined value.

### Claim 9 (depends on 1)

The CRC unit according to claim 1, further comprising a multiplexer having a first and second input coupled with a left and a right output of said shift buffer, respectively and being controlled by said control register.

### Claim 10 (depends on 1)

The CRC unit according to claim 1, wherein the shift buffer is coupled with said variable buffer memory in parallel.

### Claim 11 (depends on 1)

The CRC unit according to claim 1, wherein k is equal to four and n is equal to 32.

### Claim 12

A method for performing a cyclic redundancy check (CRC), comprising:
storing data in a variable buffer memory configured as a k-word deep and n-bit wide storage element, wherein k and m can be varied; and
moving an n-bit word in parallel into a shift buffer;
depending on a control signal serially left or right shifting the data from said shift buffer into a linear feedback shift register (LFSR) of a programmable CRC engine.

### Claim 13 (depends on 12)

The method according to claim 12, wherein the variable buffer memory is configured as a first-in first-out (FIFO) memory.

### Claim 14 (depends on 13)

The method according to claim 13, wherein each n-bit word in the variable FIFO memory comprises m bytes, wherein m can vary from 1 to Q, Q being an integer greater 1.

### Claim 15 (depends on 14)

The method according to claim 14, wherein Q=4.

### Claim 16 (depends on 14)

The method according to claim 14, further comprising the step of counting the number of data elements stored in said FIFO memory by a counter.

### Claim 17 (depends on 16)

The method according to claim 16, further comprising the step of generating an interrupt signal when the counter reaches a predetermined value.

### Claim 18 (depends on 12)

The method according to claim 12, further comprising the step of programming a control register bit to indicate the shift direction to said shift buffer.

### Claim 19 (depends on 12)

The method according to claim 12, further comprising the step of multiplexing a left and a right output of said shift buffer.

### Claim 20 (depends on 12)

The method according to claim 12, wherein k is equal to four and n is equal to 32.

### Claim 21

A cyclic redundancy check (CRC) unit, comprising:
a programmable CRC engine;
a variable first-in first-out (FIFO) memory configured as an k-word deep and n-bit wide storage element, wherein k and n can be varied; and
a controllable shift buffer coupled in parallel with said FIFO memory, a control register coupled with the shift register for setting a shift direction to either serially left or right shift data from said shift register, and a multiplexer having an output coupled with said CRC engine and a first and second input coupled with a left and a right output of said shift buffer, respectively and being controlled by said control register.