# US 8,543,877 B2 · Method of performing a chip burn-in scanning with increased efficiency

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- Number: US 8,543,877 B2
- Document ID: US8543877B2
- Status: Granted
- Kind: B2
- Application number: 13/291,041
- Filed: 2011-11-07
- Published: 2012-05-24
- Granted: 2013-09-24
- Earliest claimed: 2010-11-24
- Assignees: Etron Technology, Inc.
- Applicants: Wei-Ju Chen; Shi-Huei Liu; Lien-Sheng Yang
- Inventors: Wei-Ju Chen; Shi-Huei Liu; Lien-Sheng Yang
- Web page: https://patentgrep.com/patent/US8543877B2

## CPC

- G11C 29/06: Acceleration testing
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Utilize a pattern generator to write a predetermined logic voltage to each memory cell of a memory chip. Read a predetermined logic voltage stored in the memory cell. Compare the predetermined logic voltage stored in the memory cell with the predetermined logic voltage to determine if the memory cell is a good memory cell or not and store a determination result corresponding to the memory cell in a data latch of the memory chip. And determine if the memory chip is a good memory chip or not according to determination results of all memory cells of the memory chip stored in the data latch of the memory chip.

## Claims

### Claim 1

A method of performing chip burn-in scanning with increased efficiency, the method comprising:
utilizing a pattern generator to write a predetermined logic voltage to a plurality of memory cells of a memory chip;
reading a predetermined logic voltage stored in the plurality of memory cells;
comparing the predetermined logic voltage stored in the plurality of memory cells with the predetermined logic voltage written by the pattern generator to determine whether the plurality of memory cells are passing or not, and storing a plurality of determination results corresponding to the plurality of memory cells in a data latch of the memory chip;
executing at least one logic operation on the plurality of determination results stored in the data latch of the memory chip to generate a final logic operation result of the memory chip; and
determining whether the memory chip passes or not according to the final logic operation result and a read signal generated from a test machine.

### Claim 2 (depends on 1)

The method of claim 1, wherein the pattern generator utilizes a solid pattern to write the predetermined logic voltage to the plurality of memory cells of the memory chip.

### Claim 3 (depends on 1)

The method of claim 1, wherein the pattern generator utilizes a checkerboard pattern to write the predetermined logic voltage to the plurality of memory cells of the memory chip.

### Claim 4 (depends on 1)

The method of claim 1, wherein the pattern generator utilizes a row bar pattern to write the predetermined logic voltage to the plurality of memory cells of the memory chip.

### Claim 5 (depends on 1)

The method of claim 1, wherein the pattern generator utilizes a column bar pattern to write the predetermined logic voltage to the plurality of memory cells of the memory chip.

### Claim 6 (depends on 1)

The method of claim 1, wherein executing the at least one logic operation on the plurality of determination results stored in the data latch of the memory chip to generate the final logic operation result comprises:
executing a first logic operation on the plurality of determination results of the plurality of memory cells corresponding to each input/output terminal of a plurality of input/output terminals of the memory chip to generate a plurality of first logic operation results;
dividing the plurality of first logic operation results into a plurality of first logic operation result groups;
executing a second logic operation on the plurality of first logic operation result groups to generate a plurality of second logic operation results; and
executing a third logic operation on the plurality of second logic operation results to generate the final logic operation result of the memory chip.

### Claim 7 (depends on 6)

The method of claim 6, wherein the first logic operation, the second logic operation, or the third logic operation is an “AND” logic operation.

### Claim 8 (depends on 1)

The method of claim 1, wherein executing the at least one logic operation on the plurality of determination results stored in the data latch of the memory chip to generate the final logic operation result comprises:
executing a predetermined logic operation on the plurality of determination results to generate the final logic operation result.

### Claim 9 (depends on 8)

The method of claim 8, wherein the predetermined logic operation is an “AND” logic operation.

### Claim 10 (depends on 1)

The method of claim 1, wherein the predetermined logic voltage is a logic-high voltage.

### Claim 11 (depends on 1)

The method of claim 1, wherein the predetermined logic voltage is a logic-low voltage.