# US 8,543,874 B2 · Macro and command execution from memory array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,874 B2 - Document ID: US8543874B2 - Status: Granted - Kind: B2 - Application number: 13/651,931 - Filed: 2012-10-15 - Published: 2013-02-14 - Granted: 2013-09-24 - Earliest claimed: 2008-10-30 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Frankie F. Roohparvar; Benjamin Louie - Web page: https://patentgrep.com/patent/US8543874B2 ## CPC - G11C 29/16: using microprogrammed units, e.g. state machines - G11C 16/04: using variable threshold transistors, e.g. FAMOS - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device. Decode blocks adapted to interpret instructions and data stored in the memory device. Methods can be used to perform internal self-test operations of the memory device by executing test procedures stored in the memory array of the memory device performing a self-test operation. ## Claims ### Claim 1 A method of testing a memory device comprising: performing a read operation of a location of a first plurality of memory cells of the memory device in response to a first received command; decoding data read from the first plurality of memory cells into a first test program for testing a second plurality of memory cells of the memory device; and testing the second plurality of memory cells utilizing the first test program; wherein decoding data read from the first plurality of memory cells into the first test program comprises decoding from the data read from the first plurality of memory cells at least one of a macro, a command, and an instruction for control circuitry of the memory device to perform the testing of the second plurality of memory cells. ### Claim 2 (depends on 1) The method of claim 1, wherein the first plurality of memory cells are located in a first bank of memory cells of the memory device and the second plurality of memory cells are located in a second bank of memory cells of the memory device. ### Claim 3 (depends on 2) The method of claim 2 further comprising: performing a read operation of a location of the second bank of memory cells in response to a second received command; decoding data read from the second bank of memory cells into a second test program for testing the first bank of memory cells; and testing the first bank of memory cells utilizing the second test program. ### Claim 4 (depends on 1) The method of claim 1, wherein the first plurality of memory cells and the second plurality of memory cells are located in a same bank of memory cells of the memory device. ### Claim 5 (depends on 1) The method of claim 1, wherein performing a read operation of a location of a first plurality of memory cells further comprises reading memory cells of the location of the first plurality of memory cells as single level memory cells. ### Claim 6 (depends on 5) The method of claim 5, wherein testing the second plurality of memory cells further comprises testing the second plurality of memory cells where the second plurality of memory cells are configured to operate as multi-level memory cells. ### Claim 7 (depends on 1) The method of claim 1, further comprising storing data in the location of the first plurality of memory cells prior to performing the read operation of the location of the first plurality of memory cells. ### Claim 8 (depends on 7) The method of claim 7, wherein storing data in the location of the first plurality of memory cells further comprises storing data in the location of the first plurality of memory cells where memory cells of the location of the first plurality of memory cells are only operated as single level memory cells. ### Claim 9 (depends on 1) The method of claim 1, further comprising receiving the first received command from an external host coupled to the memory device. ### Claim 10 (depends on 1) The method of claim 1, further comprising storing data read from the first plurality of memory cells in a data cache prior to decoding the data read from the first plurality of memory cells. ### Claim 11 (depends on 1) The method of claim 1, wherein the first test program comprises one of a macro, command or instruction. ### Claim 12 (depends on 1) The method of claim 1, wherein decoding data read from the first plurality of memory cells further comprises decoding register addresses and register data from the data read from the first plurality of memory cells, and outputting the decoded register addresses and register data on an internal register address bus and register data bus of the memory device. ### Claim 13 (depends on 1) The method of claim 1, wherein testing the second plurality of memory cells further comprises testing the second plurality of memory cells by performing a read operation of data previously stored in a location of the second plurality of memory cells, and performing a comparison of the read data previously stored in the location of the second plurality of memory cells with at least a portion of the data read from the first plurality of memory cells. ### Claim 14 (depends on 13) The method of claim 13, further comprising inverting the data read from the location of the second plurality of memory cells prior to comparing with the at least a portion of the data read from the first plurality of memory cells. ### Claim 15 A method of testing a memory device comprising: storing data corresponding to a first test program in a location of a first plurality of memory cells of the memory device; performing a read operation of the data corresponding to the first test program stored in the location of the first plurality of memory cells in response to a first received command; decoding data read from the first plurality of memory cells into the first test program for testing a second plurality of memory cells of the memory device; and testing the second plurality of memory cells utilizing the first test program; wherein decoding data read from the first plurality of memory cells into the first test program comprises decoding from the data read from the first plurality of memory cells at least one of a macro, a command, and an instruction for control circuitry of the memory device to perform the testing of the second plurality of memory cells. ### Claim 16 (depends on 15) The method of claim 15, further comprising: storing data corresponding to a second test program in a location of the second plurality of memory cells of the memory device; performing a read operation of the data corresponding to the second test program stored in the location of the second plurality of memory cells in response to a second received command; decoding data read from the second plurality of memory cells into the second test program for testing the first plurality of memory cells; and testing the first plurality of memory cells utilizing the second test program. ### Claim 17 (depends on 16) The method of claim 16, wherein memory cells storing data corresponding to the first test program and memory cells storing data corresponding to the second test program comprise memory cells configured to operate as single level memory cells. ### Claim 18 (depends on 15) The method of claim 15, wherein the first test program comprises an internal self-test operation. ### Claim 19 A method of testing a memory device comprising: performing a read operation of a location of a first plurality of memory cells of the memory device in response to a first received command, where memory cells of the location of the first plurality of memory cells are configured to operate as single level memory cells; decoding data read from the first plurality of memory cells into a first test program for testing a second plurality of memory cells of the memory device; and testing the second plurality of memory cells utilizing the first test program; wherein decoding data read from the first plurality of memory cells into the first test program comprises decoding from the data read from the first plurality of memory cells at least one of a macro, a command, and an instruction for control circuitry of the memory device to perform the testing of the second plurality of memory cells. ### Claim 20 (depends on 19) The method of claim 19, wherein the second plurality of memory cells comprise memory cells configured to operate as multi-level memory cells. ### Claim 21 (depends on 19) The method of claim 19, further comprising: storing data read from the first plurality of memory cells in a first data cache of the memory device; performing a read operation of a location of the second plurality of memory cells; and storing data read from the second plurality of memory cells in a second data cache of the memory device. ### Claim 22 (depends on 21) The method of claim 21, wherein testing the second plurality of memory cells further comprises testing the second plurality of memory cells by comparing data stored in the first data cache with data stored in the second data cache.