# US 8,543,857 B2 · Method and apparatus for low power operation of multi-core processors > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,857 B2 - Document ID: US8543857B2 - Status: Granted - Kind: B2 - Application number: 12/567,755 - Filed: 2009-09-26 - Published: 2011-03-31 - Granted: 2013-09-24 - Earliest claimed: 2009-09-26 - Assignees: Intel Corporation - Applicants: Guy M. Therien - Inventors: Guy M. Therien - Web page: https://patentgrep.com/patent/US8543857B2 ## CPC - G06F 1/3203: Power management, i.e. event-based initiation of a power-saving mode - G06F 9/5094: {where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206)} - G06F 2209/5012: Processor sets - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Embodiments of an apparatus, system and method are described for low power operation of a multi-core processing system. An apparatus may comprise, for example, a power management module operative to initialize a low power mode, detect one or more un-affinitized software threads, and affinitize the one or more un-affinitized software threads to run on a set of processor cores of a multi-core processor, wherein the set of processor cores comprises less than a total number of processor cores of the multi-core processor. Other embodiments are described and claimed. ## Claims ### Claim 1 A method, comprising: receiving a request to enter a low power mode; continuously detecting one or more un-affinitized software threads for an active workload in the low power mode; detecting power or thermal characteristics for each of a plurality of cores of a multi-core processor; selecting a set of processor cores based on the detected power or thermal characteristics; continuously affinitizing the one or more detected un-affinitized software threads for the active workload to run on the selected set of processor cores of the multi-core processor, the selected set of processor cores comprising less than a total number of processor cores of the multi-core processor; successively reducing the number of processor cores in the set of processor cores; affinitizing the one or more un-affinitized software threads to run on the reduced set of processor cores; and reducing processor performance states for one or more of the processor cores in the set of processor cores. ### Claim 2 (depends on 1) The method of claim 1, comprising: applying linear throttling to one or more of the processor cores in the set of processor cores. ### Claim 3 (depends on 2) The method of claim 2, comprising: applying the linear throttling based on a utilization threshold. ### Claim 4 (depends on 1) The method of claim 1, comprising: affinitizing the one or more un-affinitized software threads to run on one of the plurality of processor cores of the multi-core processor. ### Claim 5 An apparatus, comprising: a power management module operative to receive a request to enter a low power mode, continuously detect one or more un-affinitized software threads for the low power mode, to detect power or thermal characteristics for each of a plurality of cores of a multi-core processor, to select a set of processor cores based on the detected power or thermal characteristics, to continuously affinitize the one or more detected un-affinitized software threads for the active workload to run on the selected set of processor cores of the multi-core processor, the selected set of processor cores comprising less than a total number of processor cores of the multi-core processor, to successively reduce the number of processor cores in the set of processor cores, to affinitize the one or more un-affinitized software threads to run on the reduced set of processor cores, and to reduce processor performance states for one or more of the processor cores in the set of processor cores. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the power management module is operative to apply linear throttling to one or more of the processor cores in the set of processor cores. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the power management module is operative to apply the linear throttling based on a utilization threshold. ### Claim 8 (depends on 5) The apparatus of claim 5, wherein the power management module is operative to affinitize the one or more un-affinitized software threads to run on one of the plurality of processor cores of the multi-core processor. ### Claim 9 An article comprising a computer-readable storage medium containing instructions that if executed by a processor enable a system to: receive a request to enter a low power mode; continuously detect one or more un-affinitized software threads for a low power mode; detect power or thermal characteristics for each of a plurality of cores of a multi-core processor; select a set of processor cores based on the detected power or thermal characteristics; continuously affinitize the one or more detected un-affinitized software threads to run on the selected set of processor cores of the multi-core processor, wherein the selected set of processor cores comprises less than a total number of processor cores of the multi-core processor; successively reduce the number of processor cores in the set of processor cores; affinitize the one or more un-affinitized software threads to run on the reduced set of processor cores; and reducing processor performance states for one or more of the processor cores in the set of processor cores. ### Claim 10 (depends on 9) The article of claim 9, comprising instructions that if executed enable the system to apply linear throttling to one or more of the processor cores in the set of processor cores. ### Claim 11 (depends on 10) The article of claim 10, comprising instructions that if executed enable the system to apply the linear throttling based on a utilization threshold. ### Claim 12 (depends on 9) The article of claim 9, comprising instructions that if executed enable the system to affinitize the one or more un-affinitized software threads to run on one of the plurality of processor cores of the multi-core processor. ### Claim 13 A system, comprising: a multi-core processor; and a power management module operative to receive a request to enter a low power mode, continously detect one or more un-affinitized software threads for a low power mode, to detect power or thermal characteristics for each of a plurality of cores of a multi-core processor, to select a set of processor cores based on the detected power or thermal characteristics, to continously affinitize the one or more detected un-affinitized software threads to run on the selected set of processor cores of the multi-core processor, the selected set of processor cores comprising less than a total number of processor cores of the multi-core processor, to successively reduce the number of processor cores in the set of processor cores, to affinitize the one or more un-affinitized software threads to run on the reduced set of processor cores, and to reduce processor performance states for one or more of the processor cores in the set of processor cores. ### Claim 14 (depends on 13) The system of claim 13, wherein the power management module is operative to apply linear throttling to one or more of the processor cores in the set of processor cores. ### Claim 15 (depends on 14) The system of claim 14, wherein the power management module is operative to apply the linear throttling based on a utilization threshold. ### Claim 16 (depends on 13) The system of claim 13, wherein the power management module is operative to affinitize the one or more un-affinitized software threads to run on one of the plurality of processor cores of the multi-core processor. ### Claim 17 (depends on 13) The system of claim 13, comprising: a volatile memory to store the power management module.