# US 8,543,856 B2 · Semiconductor device with wake-up unit

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- Number: US 8,543,856 B2
- Document ID: US8543856B2
- Status: Granted
- Kind: B2
- Application number: 13/214,164
- Filed: 2011-08-20
- Published: 2013-02-21
- Granted: 2013-09-24
- Earliest claimed: 2011-08-20
- Assignees: Freescale Semiconductor, Inc.
- Applicants: Shubhra Singh; Kumar Abhishek; Mukesh Bansal
- Inventors: Shubhra Singh; Kumar Abhishek; Mukesh Bansal
- Web page: https://patentgrep.com/patent/US8543856B2

## CPC

- G06F 1/3206: Monitoring of events, devices or parameters that trigger a change in power modality
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A semiconductor device having a low power mode includes a buffer circuit associated with an interface pad, a power management controller (PMC), and a wakeup unit for waking up a part of the device from the low power mode. The buffer circuit is disabled in the low power mode by asserting a power on reset (POR) signal associated with the PMC. A wakeup signal is generated and provided to the wakeup unit from an analog power supply associated with the buffer circuit.

## Claims

### Claim 1

A semiconductor device having a plurality of I/O pads, wherein the semiconductor device is operable in a low power mode, the semiconductor device comprising:
at least one interface pad;
a buffer circuit connected to the interface pad, wherein the buffer circuit includes,
an input buffer having an input terminal connected to the interface pad for receiving a signal input to the interface pad,
an output buffer having an output terminal connected to the interface pad and the input terminal of the input buffer, for transmitting a signal to the interface pad, and
a resistor having a first terminal connected to the interface pad, the input terminal of the input buffer, and the output terminal of the output buffer, and a second terminal for providing a wake-up signal;
a power management controller (PMC) coupled to said I/O pads and said interface pad for supplying power thereto, wherein power to said I/O pads and said interface pad is disabled during said low power mode by assertion of a power on reset signal of said PMC;
a first level shifter, connected to the second terminal of the resistor of the buffer circuit, for receiving the wake-up signal and shifting a voltage level of the wake-up signal from a analog supply high operation voltage level to a core operation voltage level; and
a wake-up unit connected to the first level shifter for receiving the level-shifted wake-up signal, wherein the wake-up unit wakes up at least a part of said semiconductor device from said low power mode.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, further comprising:
a memory for storing package personality data including I/O pad usage data;
a second level shifter connected to the memory for shifting an output of the memory from a low voltage level to a high voltage level; and
a logic gate connected between the first level shifter and the buffer circuit, wherein the logic gate has a first input terminal that receives the wake-up signal and a second input connected to the second level shifter for receiving the level shifted memory output, and an output terminal connected to an the input of the first level shifter.