# US 8,543,843 B1 · Virtual core management

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- Number: US 8,543,843 B1
- Document ID: US8543843B1
- Status: Granted
- Kind: B1
- Application number: 11/933,349
- Filed: 2007-10-31
- Granted: 2013-09-24
- Earliest claimed: 2006-03-29
- Assignees: Sun Microsystems, Inc.; Sun Microsystems Technology Ltd.
- Applicants: Yu Qing Cheng; John Gregory Favor; Peter N. Glaskowsky; Carlos Puchol; Seungyoon Peter Song
- Inventors: Yu Qing Cheng; John Gregory Favor; Peter N. Glaskowsky; Carlos Puchol; Seungyoon Peter Song
- Web page: https://patentgrep.com/patent/US8543843B1

## CPC

- G06F 9/3851: {from multiple instruction streams, e.g. multistreaming}
- G06F 9/3888: {controlled by a single instruction for multiple threads [SIMT] in parallel}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A virtual core management system including one or more physical cores, a virtual core including a collection of logical states associated with the execution of a program, and a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations.

## Claims

### Claim 1

A system adapted for use with a computer processor having a bus unit and one or more physical processor cores, the system comprising:
a memory component adapted to store one or more virtual cores; and
a virtual core management component adapted to map the one or more virtual cores to at least one of the physical cores to enable an execution of one or more programs,
wherein the virtual core management component is configured to unmap one or more virtual cores from one or more physical cores in response to one or more virtual cores being put into a sleep state,
wherein the one or more virtual cores include one or more logical states associated with the execution of the one or more programs,
wherein the mapping comprises transferring the one or more logical states of the one or more virtual cores from the memory component to the at least one physical core, and wherein the virtual core management component comprises a transaction redirection component adapted to route signals between the one or more physical cores and the bus unit based on the mapping of the virtual core.

### Claim 2

A virtual core management system comprising:
one or more physical cores;
a virtual core including a collection of logical states associated with the execution of a program; and
a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations,
wherein the virtual core management component is configured to unmap the virtual core from a physical core in response to the virtual core being put into a sleep state, and
wherein the virtual core management component comprises a transaction redirection component adapted to route signals between the one or more physical cores and a bus unit based on the mapping of the virtual core.

### Claim 3 (depends on 2)

The virtual core management system of claim 2, wherein the virtual core management component maps the virtual core to a higher performance physical core when the program requires high performance.

### Claim 4 (depends on 2)

The virtual core management system of claim 2, wherein the virtual core management component maps the virtual core with a lower power physical core when the program does not require high performance.

### Claim 5 (depends on 2)

The virtual core management system of claim 2, wherein the virtual core management component maps the virtual core with a lower power physical core when the program requires low power consumption.

### Claim 6 (depends on 2)

The virtual core management system of claim 2, wherein the virtual core management component maps the virtual core with a more energy-efficient physical core when the program requires high energy efficiency.

### Claim 7 (depends on 2)

The virtual core management system of claim 2, wherein a voltage on the unmapped physical core is lowered to reduce power consumption.

### Claim 8 (depends on 7)

The virtual core management system of claim 7, wherein the voltage is lowered to zero.

### Claim 9 (depends on 2)

The virtual core management system of claim 2, wherein the virtual core management component unmaps the virtual core from the physical core based upon an ACPI request.

### Claim 10

A method for use in a processing system comprising:
providing one or more physical cores and a virtual core, the virtual core including a collection of logical states associated with the execution of a program;
mapping the virtual core to at least one of the one or more physical cores based upon power management considerations;
unmapping the virtual core from a physical core in response to the virtual core being put into a sleep state; and
routing signals between the one or more physical cores and a bus unit based on the mapping of the virtual core using a transaction redirection component.

### Claim 11 (depends on 10)

The method of claim 10, wherein the virtual core can be mapped to a higher performance physical core when the program requires high performance.

### Claim 12 (depends on 10)

The method of claim 10, wherein the virtual core can be mapped to a lower power physical core when the program does not require high performance.

### Claim 13 (depends on 10)

The method of claim 10, wherein the virtual core can be mapped to a lower power physical core when the program requires low power consumption.

### Claim 14 (depends on 10)

The method claim 10, wherein the virtual core can be mapped with a more energy efficient physical core when the program requires high energy efficiency.

### Claim 15 (depends on 10)

The method of claim 10, wherein a voltage on the unmapped physical core is lowered to reduce power consumption.

### Claim 16 (depends on 15)

The method of claim 15, wherein the voltage is lowered to zero.

### Claim 17 (depends on 10)

The method of claim 10, wherein the virtual core is unmapped from the physical core based upon an ACPI request.

### Claim 18

A non-transitory computer-readable medium that includes a circuit description of a virtual core management system, wherein the circuit description when interpreted by a computer system specifies the virtual core management system comprising:
one or more physical cores;
a virtual core including a collection of logical states associated with the execution of a program; and
a virtual core management component configured to map the virtual core to one of the one or more physical cores based upon power management considerations,
wherein the virtual core management component is configured to unmap the virtual core from a physical core in response to the virtual core being put into a sleep state, and
wherein the virtual core management component comprises a transaction redirection component adapted to route signals between the one or more physical cores and a bus unit based on the mapping of the virtual core.

### Claim 19 (depends on 2)

The virtual core management system of claim 2, wherein the virtual core management component further comprises:
a virtual control management control unit adapted to communicate with the one or more physical cores;
a virtual advanced programmable interrupt controller (vAPIC) adapted to accept and process transactions received from the bus unit; and
a monitor adapted to monitor one or more areas of memory based on one or more physical cores and adapted to communicate with one or more physical cores when access is completed to a portion of monitored memory with intent to write.

### Claim 20 (depends on 10)

The method of claim 10, wherein mapping of the virtual core to one of the one or more physical cores based upon power considerations is done with a virtual core management component and the method further comprising:
communicating with the one or more physical cores using a virtual control management control unit;
accepting and processing transactions received from the bus unit using a virtual advanced programmable interrupt controller (vAPIC); and
monitoring, with a monitor, one or more areas of memory based on one or more physical cores and adapted to communicate with one or more physical cores when access is completed to a portion of monitored memory with intent to write.