# US 8,543,796 B2 · Optimizing performance of instructions based on sequence detection or information associated with the instructions

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- Number: US 8,543,796 B2
- Document ID: US8543796B2
- Status: Granted
- Kind: B2
- Application number: 12/290,962
- Filed: 2008-11-05
- Published: 2010-05-06
- Granted: 2013-09-24
- Earliest claimed: 2008-11-05
- Assignees: Intel Corporation
- Applicants: Ohad Falik; Lihu Rappoport; Ron Gabor; Yulia Kurolap; Michael Mishaeli
- Inventors: Ohad Falik; Lihu Rappoport; Ron Gabor; Yulia Kurolap; Michael Mishaeli
- Web page: https://patentgrep.com/patent/US8543796B2

## CPC

- G06F 9/30145: {Instruction analysis, e.g. decoding, instruction word fields}
- G06F 9/30032: {Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE}
- G06F 9/30043: {LOAD or STORE instructions; Clear instruction}
- G06F 9/3017: {Runtime instruction translation, e.g. macros}
- G06F 9/30181: {Instruction operation extension or modification}
- G06F 9/325: {for loops, e.g. loop detection or loop counter}
- G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating}
- G06F 9/3856: {Reordering of instructions, e.g. using queues or age tags}
- G06F 9/3858: {Result writeback, i.e. updating the architectural state or memory}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.

## Claims

### Claim 1

An apparatus comprising:
an execution unit to perform operations indicated by instruction codes; and
an instruction decoder to decode a first incoming instruction into a first instruction code or a second instruction code based on a path select signal indicative of detection of a sequence of instructions, wherein the instruction decoder is to receive the path select signal from a sequence detector coupled to the instruction decoder, the path select signal having a second state to correspond to detection of a second incoming instruction used in conjunction with the first incoming instruction and received in the instruction decoder within a threshold distance of the first incoming instruction, the instruction decoder to decode the first incoming instruction into the first instruction code to cause the execution unit to run a first optimized operation responsive to the path select signal having a first state and to otherwise decode the first incoming instruction into the second instruction code to cause the execution unit to run a second optimized operation responsive to the path select signal having the second state.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising a comparator to receive an instruction code from the instruction decoder and an expected code from the sequence detector and to generate a match signal if the instruction code and the expected code match.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the sequence detector is to generate the path select signal of the first state to cause the instruction decoder to decode the first incoming instruction into the first instruction code if the match signal is not generated, the first instruction code corresponding to a copy operation optimized for a first data length.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein the sequence detector is to generate the path select signal of the second state to cause the instruction decoder to decode the first incoming instruction into the second instruction code responsive to the match signal, the second instruction code corresponding to the copy operation optimized for a second data length different than the first data length.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the second instruction code is to cause the execution unit to perform the copy operation of a limited length.

### Claim 6 (depends on 4)

The apparatus of claim 4, wherein the sequence detector is to generate the path select signal of the second state if the second incoming instruction is received by the instruction decoder within a first number of instructions corresponding to the threshold distance from the first incoming instruction.

### Claim 7 (depends on 6)

The apparatus of claim 6, wherein the threshold distance is approximated by a number of cycles and decode stall information.

### Claim 8 (depends on 6)

The apparatus of claim 6, wherein the sequence detector includes a state machine, the state machine to reset if the different incoming instruction is not received within the first number of instructions.

### Claim 9

A system comprising:
a processor having a front end including a decoder to decode an incoming copy instruction into a first instruction code or a second instruction code based on a select signal generated by a sequence detector, the select signal having a second state indicative of a receipt of a sequence of instructions in the decoder including the incoming copy instruction and at least one other copy instruction, the decoder to decode the incoming copy instruction into the second instruction code responsive to the select signal having the second state and otherwise to decode the first incoming copy instruction into a first instruction code, the processor further having an execution unit to receive the first or second instruction code and to perform a first copy operation or a second copy operation respectively, responsive thereto; and
a dynamic random access memory (DRAM) coupled to the processor.

### Claim 10 (depends on 9)

The system of claim 9, the sequence detector to generate the select signal having the second state to cause the decoder to generate the second instruction code if the incoming copy instruction is received within a first number of instructions after a second incoming copy instruction corresponding to the at least one other copy instruction, and to otherwise cause the decoder to generate the first instruction code.

### Claim 11 (depends on 10)

The system of claim 10, wherein the sequence detector is to reset to a first state to search for the second incoming copy instruction if the incoming copy instruction is not received within the first number of instructions.

### Claim 12 (depends on 11)

The system of claim 11, wherein the sequence detector is to advance from the first state to the second state to search for the incoming copy instruction after the second incoming copy instruction is detected.

### Claim 13 (depends on 10)

The system of claim 10, further comprising a comparator to receive an instruction code from the decoder and an expected code from the sequence detector and to generate a match signal if the instruction code and the expected code match.

### Claim 14 (depends on 9)

The system of claim 9, wherein the first copy operation is optimized for a first data length, and the second copy operation is optimized for a second data length different from the first data length.