# US 8,543,793 B2 · Maintaining processor resources during architectural events

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 8,543,793 B2
- Document ID: US8543793B2
- Status: Granted
- Kind: B2
- Application number: 13/020,161
- Filed: 2011-02-03
- Published: 2011-05-26
- Granted: 2013-09-24
- Earliest claimed: 2004-07-30
- Assignees: Intel Corporation
- Applicants: Jason W. Brandt; Sanjoy K. Mondal; Richard Uhlig; Gilbert Neiger; Robert T. George
- Inventors: Jason W. Brandt; Sanjoy K. Mondal; Richard Uhlig; Gilbert Neiger; Robert T. George
- Web page: https://patentgrep.com/patent/US8543793B2

## CPC

- G06F 12/1036: for multiple virtual address spaces, e.g. segmentation (G06F12/1045 takes precedence)
- G06F 9/45533: {Hypervisors; Virtual machine monitors}
- G06F 9/45558: {Hypervisor-specific management and integration aspects}
- G06F 9/4843: {by program, e.g. task dispatcher, supervisor, operating system}
- G06F 12/0292: {using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10)}
- G06F 12/0804: with main memory updating (G06F12/0806 takes precedence)
- G06F 12/0891: using clearing, invalidating or resetting means
- G06F 12/1027: using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]
- G06F 12/1063: {the data cache being concurrently virtually addressed}
- G06F 12/109: for multiple virtual address spaces, e.g. segmentation (G06F12/1036 takes precedence)
- G06F 12/12: Replacement control
- G06F 12/123: with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
- G06F 2009/45583: {Memory management, e.g. access or allocation}
- G06F 2009/45591: {Monitoring or debugging support}
- G06F 2212/1016: Performance improvement
- G06F 2212/1024: Latency reduction
- G06F 2212/152: Virtualized environment, e.g. logically partitioned system
- G06F 2212/30: Providing cache or TLB in specific location of a processing system
- G06F 2212/50: Control mechanisms for virtual memory, cache or TLB
- G06F 2212/604: Details relating to cache allocation
- G06F 2212/651: Multi-level translation tables
- G06F 2212/657: Virtual address space management
- G06F 2212/68: Details of translation look-aside buffer [TLB]
- G06F 2212/683: Invalidation
- G06F 2212/684: TLB miss handling
- G06F 2212/70: Details relating to dynamic memory management
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

## Claims

### Claim 1

A processor comprising:
a control register to store a page directory base address corresponding to an address space;
a translation lookaside buffer having entries including an address space identifier field; and
execution logic to determine whether the address space exists in a list of active address spaces in response to a move to control register instruction, and to switch between address spaces without flushing the translation lookaside buffer in response to a determination that the address space is present in the list of active address spaces.

### Claim 2 (depends on 1)

The processor of claim 1, wherein the control register is CR3.

### Claim 3 (depends on 1)

The processor of claim 1, wherein the execution logic is also to switch between a first process and a second process without flushing the translation lookaside buffer.

### Claim 4 (depends on 1)

The processor of claim 1, wherein the execution logic is also to switch between a first guest and a second guest without flushing the translation lookaside buffer.

### Claim 5 (depends on 1)

The processor of claim 1, wherein the translation lookaside buffer is to store address space identifiers (ASIDs).

### Claim 6 (depends on 1)

The processor of claim 1, wherein the address space identifier field includes a plurality of bits.

### Claim 7 (depends on 3)

The processor of claim 3, wherein the execution logic is also to flush the translation lookaside buffer in response to switching to a third process.

### Claim 8

A method comprising:
storing, in a control register, a page directory base address corresponding to an address space;
storing, in a translation lookaside buffer, an address space identifier;
determining whether the address space exists in a list of active address spaces in response to a move to control register instruction; and
executing the move to control register instruction to switch between address spaces without flushing the translation lookaside buffer in response to a determination that the address space is present in the list of active address spaces.

### Claim 9 (depends on 8)

The method of claim 8, wherein the control register is CR3.

### Claim 10 (depends on 8)

The method of claim 8, further comprising switching between a first process and a second process without flushing the translation lookaside buffer.

### Claim 11 (depends on 8)

The method of claim 8, further comprising switching between a first guest and a second guest without flushing the translation lookaside buffer.

### Claim 12 (depends on 8)

The method of claim 8, wherein the address space identifier includes a plurality of bits.

### Claim 13 (depends on 10)

The method of claim 10, further comprising flushing the translation lookaside buffer in response to switching to a third process.

### Claim 14

A processor to execute a virtual machine monitor, the virtual machine monitor to present one or more virtual machines to guest software, the processor comprising:
a control register to store a page directory base address corresponding to an address space;
a translation lookaside buffer having entries including an address space identifier field; and
an execution logic to determine whether the address space of a second guest exists in a list of active address spaces in response to a move to control register instruction, and to switch between the address space of a first guest and the address space of the second guest without flushing the translation lookaside buffer in response to a determination that the address space of the second guest is present in the list of active address spaces, the address space of the first guest corresponding to a first address space identifier and the address space of the second guest corresponding to a second address space identifier.

### Claim 15 (depends on 14)

The processor of claim 14, wherein the execution logic is also to flush the translation lookaside buffer in response to switching to a third guest.