# US 8,543,787 B2 · Non-volatile memory circuit, system, and method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,787 B2 - Document ID: US8543787B2 - Status: Granted - Kind: B2 - Application number: 12/148,521 - Filed: 2008-04-17 - Published: 2008-10-23 - Granted: 2013-09-24 - Earliest claimed: 2007-04-17 - Assignees: Micron Technology, Inc. - Applicants: Daniele Balluchi; Graziano Mirichigni - Inventors: Daniele Balluchi; Graziano Mirichigni - Web page: https://patentgrep.com/patent/US8543787B2 ## CPC - G06F 3/0604: {Improving or facilitating administration, e.g. storage management} - G06F 3/0629: {Configuration or reconfiguration of storage systems} - G06F 3/0685: {Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays} - G06F 12/0638: {Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module (address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70)} - G11C 7/1015: {Read-write modes for single port memories, i.e. having either a random port or a serial port} - G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits} - G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 16/102: {External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators} - G06F 2212/2022: Flash memory - G11C 16/32: Timing circuits - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract A non volatile memory device includes a first buffer register configured to receive and store the data to be stored into the memory device provided via a memory bus. A command window is activatable for interposing itself for access to a memory matrix between the first buffer element and the memory matrix. The command window includes a second buffer element that stores data stored in or to be stored into a group of memory elements. A first data transfer means executes a first transfer of the data stored in the second buffer register into the first buffer register during a first phase of a data write operation started by the reception of a first command. A second data transfer means receives the data provided by the memory bus and modifies, based on the received data, the data stored in the first buffer register during a second phase of the data write operation started by the reception of a second command. The first transfer means execute a second transfer of the modified data stored in the first buffer register into the second buffer register during a third phase of the data write operation. The second transfer is executed in response to the reception of a signal received by the memory bus together with the second command. ## Claims ### Claim 1 A non-volatile memory device couplable with a memory bus adapted to provide data to be stored into the memory device and commands to be executed by the memory device, said memory device comprising: a memory matrix including memory elements adapted to memorize the data in a non-volatile way; at least a first buffer register configured to receive and memorize in a volatile way the data to be stored into the memory device provided by the memory bus; a command window activatable to operatively interpose itself, for the access to the memory matrix, between said at least one first buffer register and said memory matrix, said command window including at least one second buffer register adapted to store in a volatile way data memorized or to be memorized in a group of memory elements; first data transfer means adapted to execute a first transfer of the data stored in the at least one second buffer register to the at least one first buffer register during a first phase of a writing operation of the data into the memory device started by the reception of a first command; second data transfer means adapted to receive the data provided by the memory bus and modify, according to the received data, the data stored in the at least one first buffer register during a second phase of the writing operation of the data started by the reception of a second command, wherein the first transfer means are adapted to execute a second transfer of the modified data stored in the at least one first buffer register to the at least one second buffer register during a third phase of the writing operation of the data, said second transfer being executed in response to the reception of a signal received by the memory bus together with the second command. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the memory elements of the memory matrix are arranged according to a plurality of rows and a plurality of columns, and a group of memory elements comprises all the memory elements of a matrix row. ### Claim 3 (depends on 2) The memory device of claim 2, wherein said at least one first buffer register is adapted to memorize the data memorizable into a group of memory elements. ### Claim 4 (depends on 3) The memory device of claim 3, wherein said second phase of the writing operation comprises at least two phases, during each one of which a respective portion of the data to be stored into the memory device is provided by the memory bus and stored into the at least one register, said signal being provided, at the start of the last of said at least two phases. ### Claim 5 (depends on 4) The memory device of claim 4, wherein: said at least one first buffer register comprises a first plurality of buffer registers, said first and second transfer means being adapted to select a buffer register of said first plurality during the first and second phase of the writing operation; and said at least one second buffer register comprises a second plurality of buffer registers, said first transfer means being adapted to select a buffer register of said first plurality during the third phase of the writing operation. ### Claim 6 (depends on 5) The memory device of claim 5, wherein said signal includes a flag bit provided together with the second command that starts the last of said at least two phases. ### Claim 7 (depends on 6) The memory device of claim 6, wherein: the memory elements of the memory matrix are associated with a first memory space, the memory elements of each row of the matrix being associated with a corresponding subspace of the first memory space addressable by means of a corresponding first row address; the second plurality of buffer registers is associated with a second memory space, each register of the second plurality being associated with a corresponding subspace of the second memory space addressable by means of a corresponding second row address. ### Claim 8 (depends on 7) The memory device of claim 7, wherein the memory bus is adapted to provide a first row address, the data to be stored into the memory device being to be stored into the memory elements of the matrix row corresponding to the first row address. ### Claim 9 (depends on 8) The memory device of claim 8, wherein the data to be stored into the memory device are stored into a corresponding buffer register of the second plurality during the first data writing phase if the second address of said buffer register of the second plurality coincides with the first row address provided by the memory bus. ### Claim 10 (depends on 9) The memory device of claim 9, wherein said memory device is adapted to be coupled to a memory bus of the DDR type. ### Claim 11 (depends on 9) The memory device of claim 9, wherein said memory device is adapted to be coupled to a memory bus of the DDR2 type. ### Claim 12 An electronic system comprising: at least one non-volatile memory device, the memory device comprising, a memory matrix including memory elements adapted to memorize the data in a non-volatile way; at least a first buffer register configured to receive and memorize in a volatile way the data to be stored into the memory device provided by the memory bus; a command window activatable to operatively interpose itself, for the access to the memory matrix, between said at least one first buffer register and said memory matrix, said command window including at least one second buffer register adapted to store in a volatile way data memorized or to be memorized in a group of memory elements; first data transfer means adapted to execute a first transfer of the data stored in the at least one second buffer register to the at least one first buffer register during a first phase of a writing operation of the data into the memory device started by the reception of a first command; second data transfer means adapted to receive the data provided by the memory bus and modify, according to the received data, the data stored in the at least one first buffer register during a second phase of the writing operation of the data started by the reception of a second command, wherein the first transfer means are adapted to execute a second transfer of the modified data stored in the at least one first buffer register to the at least one second buffer register during a third phase of the writing operation of the data, said second transfer being executed in response to the reception of a signal received by the memory bus together with the second command; at least one volatile memory device; and a memory controller coupled with the non-volatile memory device and with the volatile memory device by means of the memory bus, said memory controller being adapted to provide data to be stored or receive data stored in the non-volatile memory device or in the volatile memory device, respectively. ### Claim 13 A method of storing data in a non-volatile memory device, the method comprising: receiving and storing data in at least one first buffer register; activating a command window interposed between the at least one first buffer register and the non-volatile memory device; receiving a first command; in response to the first command, executing a first transfer of data stored in at least one second buffer register to the at least one first buffer register during a first phase of a writing operation of the data into the non-volatile memory; receiving a second command; and in response to the second command, modifying the data stored in the at least one first buffer register during a second phase of the writing operation. ### Claim 14 (depends on 13) The method of claim 13, further comprising selecting the at least one first buffer register and the at least one second buffer register to comprise volatile memory devices thereby allowing the data to be written with a granularity of bytes. ### Claim 15 (depends on 13) The method of claim 13, further comprising setting a base address of the command window. ### Claim 16 (depends on 15) The method of claim 15, wherein the base address corresponds to a particular row address of the non-volatile memory device for which the command window overlaps the non-volatile memory device. ### Claim 17 (depends on 15) The method of claim 15, further comprising selecting the base address to overlap different portions of the non-volatile memory device. ### Claim 18 A method of storing data in a non-volatile memory device, the method comprising: receiving and storing data in at least one volatile first buffer register; activating a command window interposed between the at least one first volatile buffer register and the non-volatile memory device; executing a first transfer of data stored in at least one second volatile buffer register located within the command window to the at least one first volatile buffer register during a first phase of a writing operation of the data into the non-volatile memory upon the receiving of a first command; and modifying the data stored in the at least one first volatile buffer register during a second phase of the writing operation upon the receiving of a second command. ### Claim 19 (depends on 18) The method of claim 18, further comprising transferring the data from the at least one second volatile buffer register to the non-volatile memory device during a subsequent operation. ### Claim 20 (depends on 18) The method of claim 18, further comprising executing a second transfer of the modified data stored in the at least one first volatile buffer register to the at least one second volatile buffer register during a third phase of the writing operation of the data in response to receiving a signal.