# US 8,543,776 B2 · On-die logic analyzer for semiconductor die > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,776 B2 - Document ID: US8543776B2 - Status: Granted - Kind: B2 - Application number: 13/665,198 - Filed: 2012-10-31 - Published: 2013-02-28 - Granted: 2013-09-24 - Earliest claimed: 2009-08-14 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Tina C. Zhong; Jason G. Sandri; Kenneth P. Griesser; Lori R. Borger - Web page: https://patentgrep.com/patent/US8543776B2 ## CPC - G01R 31/3177: Testing of logic operation, e.g. by logic analysers - G01R 31/31705: {Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits (generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544)} - G01R 31/318511: {Wafer Test} - G01R 31/318513: {Test of Multi-Chip-Moduls} - G01R 31/319: Tester hardware, i.e. output processing circuits - G06F 11/079: {Root cause analysis, i.e. error or fault diagnosis (in a hardware test environment G06F11/22; in a software test environment G06F11/36)} - G06F 11/25: Testing of logic operation, e.g. by logic analysers - G06F 11/3003: {Monitoring arrangements specially adapted to the computing system or computing system component being monitored} - G06F 11/3089: {Monitoring arrangements determined by the means or processing involved in sensing the monitored data, e.g. interfaces, connectors, sensors, probes, agents (software debugging using additional hardware using a specific debug interface G06F11/3656; performance evaluation by tracing or monitoring G06F11/3466)} - G06F 11/364: {tracing values on a bus} - G06F 11/3648: {using additional hardware} - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed. ## Claims ### Claim 1 An apparatus comprising: a memory to store data, the memory partitioned into at least a first storage, a second storage, and a third storage, wherein each storage is dedicated to a corresponding agent of a system associated with the memory, and when a first agent corresponding to the first storage is inactive, the first storage is configured to be dynamically combined with the second storage to store data of a second agent corresponding to the second storage, wherein the second storage is a primary queue for the second agent and the first storage is a secondary queue for the second agent, and further when a third agent corresponding to the third storage is inactive, the third storage is configured to be dynamically combined with the second storage, wherein the first storage has a higher priority than the third storage for storage of data associated with the second agent; and a controller including a table to indicate a priority for the dynamic combining between the first storage and the third storage, with respect to the second storage. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the memory is to store trace information associated with debug or test operations of the system including the first agent and the second agent. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the controller is to receive activity information regarding the system agents and to dynamically combine the first storage and the second storage based on the activity information. ### Claim 4 (depends on 1) The apparatus of claim 1, further comprising a match function to receive information from an interconnect coupled between the first agent and the second agent and to store the information in the memory if the data matches a predetermined pattern, and otherwise to not store the information. ### Claim 5 (depends on 1) The apparatus of claim 1, further comprising a filter function to receive the data from an interconnect coupled between the first agent and the second agent and to prevent information associated with a first predetermined address from being stored in the memory and to allow information associated with a second predetermined address to be stored in the memory. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the memory is to store the data communicated between the first agent and the second agent in the first storage with a time stamp if the data is of a different state than a previous data communicated between the first agent and the second agent, and to prevent the storage if the data is of the same state as the previous data, the time stamp to enable correlation to other events occurring in the apparatus. ### Claim 7 A method comprising: partitioning a memory into at least a first storage, a second storage, and a third storage, wherein each storage is dedicated to a corresponding agent of a system associated with the memory; dynamically combining the first storage with the second storage to store data of a second agent corresponding to the second storage when a first agent corresponding to the first storage is inactive, wherein the second storage is a primary queue for the second agent and the first storage is a secondary queue for the second agent, and dynamically combining the third storage with the second storage when a third agent corresponding to the third storage is inactive, wherein the first storage has a higher priority than the third storage for storage of data associated with the second agent; and indicating a priority for the dynamic combining between the first storage and the third storage, with respect to the second storage. ### Claim 8 (depends on 7) The method of claim 7, further comprising storing trace information associated with debug or test operations of the system including the first agent and the second agent, the first agent corresponding to a processor and the second agent corresponding to a chipset. ### Claim 9 (depends on 8) The method of claim 8, further comprising receiving activity information regarding the system agents and dynamically combining the first storage and the second storage based on the activity information. ### Claim 10 A system on a chip (SoC) comprising: a processor; a chipset coupled to the processor via an interconnect; an on-die logic analyzer (ODLA) to monitor information communicated between the processor and the chipset, the ODLA including: a memory to store data, the memory partitioned into at least a first storage, a second storage, and a third storage, wherein each storage is dedicated to a corresponding agent of the SoC, and when a first agent corresponding to the first storage is inactive, the first storage is configured to be dynamically combined with the second storage of the memory to store data of a second agent corresponding to the second storage, wherein the second storage is a primary queue for the second agent and the first storage is a secondary queue for the second agent, and when a third agent corresponding to the third storage is inactive, the third storage is to be dynamically combined with the second storage, the first storage having a higher priority than the third storage for storage of data associated with the second agent; and a controller including a table to indicate a priority for the dynamic combining between the first storage and the third storage, with respect to the second storage. ### Claim 11 (depends on 10) The SoC of claim 10, wherein the ODLA is implemented within the chipset. ### Claim 12 (depends on 10) The SoC of claim 10, wherein the memory is to store trace information associated with debug or test operations.