# US 8,543,775 B2 · Preventing unintended loss of transactional data in hardware transactional memory systems > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,775 B2 - Document ID: US8543775B2 - Status: Granted - Kind: B2 - Application number: 13/714,132 - Filed: 2012-12-13 - Published: 2013-04-25 - Granted: 2013-09-24 - Earliest claimed: 2010-11-15 - Assignees: Advanced Micro Devices, Inc. - Applicants: Advanced Micro Devices, Inc. - Inventors: Jaewoong Chung; David S Christie; Michael Hohmuth; Stephan Diestelhorst; Martin Pohlack; Luke Yen - Web page: https://patentgrep.com/patent/US8543775B2 ## CPC - G06F 12/00: Accessing, addressing or allocating within memory systems or architectures (digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06) - G06F 9/3004: {to perform operations on memory} - G06F 9/30087: {Synchronisation or serialisation instructions} - G06F 9/38: Concurrent instruction execution, e.g. pipeline or look ahead - G06F 9/3834: {Maintaining memory consistency} - G06F 9/3854: {Instruction completion, e.g. retiring, committing or graduating} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method and apparatus are disclosed for implementing early release of speculatively read data in a hardware transactional memory system. A processing core comprises a hardware transactional memory system configured to receive an early release indication for a specified word of a group of words in a read set of an active transaction. The early release indication comprises a request to remove the specified word from the read set. In response to the early release request, the processing core removes the group of words from the read set only after determining that no word in the group other than the specified word has been speculatively read during the active transaction. ## Claims ### Claim 1 A method, comprising: entering, by a processor, a speculative execution mode; speculatively reading, by the processor, a first word in a cache line as part of a transaction; speculatively reading, by the processor, a second word in the cache line as part of the transaction; detecting, by the processor, an instruction specifying release of at least one of the first word and the second word from a read set; and preventing, by the processor, the release of the at least one of the first word and the second word from the read set when the first word and the second word are not the same word. ### Claim 2 (depends on 1) The method of claim 1, further comprising: adding, by a hardware transactional memory, the cache line to the read set of the transaction. ### Claim 3 (depends on 1) The method of claim 1, further comprising: setting, by the hardware transactional memory, a first flag to a value indicating the first word. ### Claim 4 (depends on 3) The method of claim 3, further comprising: reading, by the hardware transactional memory, the first flag to determine if the second word is the same as the first word. ### Claim 5 (depends on 1) The method of claim 1, further comprising: setting, by the hardware transactional memory, in response to the second word being not the same as the first word, a second flag to a value indicating that the first word and the second word have been speculatively read during the transaction. ### Claim 6 (depends on 1) The method of claim 1, further comprising: reading, by the hardware transactional memory, the second flag. ### Claim 7 (depends on 1) (New The method of claim 1, wherein adding the cache line to the read set comprises setting an SR bit of the cache line. ### Claim 8 (depends on 1) The method of claim 1, wherein the first flag is set to a binary value according to a 0-indexing scheme. ### Claim 9 (depends on 1) The method of claim 1, wherein at least one of the first flag or the second flag are stored in a Bloom filter. ### Claim 10 (depends on 9) The method of claim 9, wherein at least one of speculatively reading the first word or speculatively reading the second word comprises applying a hash function to the address of the first word or the second word. ### Claim 11 (depends on 10) The method of claim 10, wherein the hash function is a modulo function. ### Claim 12 (depends on 11) The method of claim 11, wherein the Bloom filter has a number of indices M, and the method further comprises deriving an identifier for the address by shifting the address by log2(M) bits. ### Claim 13 An apparatus, comprising: a processor configured to enter a speculative execution mode, speculatively read a first word in a cache line as part of a transaction, speculatively read a second word in the cache line as part of the transaction, detect an instruction specifying release of at least one of the first word and the second word from a read set; and prevent the release of the at least one of the first word and the second word from the read set when the first word and the second word are not the same word. ### Claim 14 (depends on 13) The apparatus of claim 13, further comprising: a hardware transactional memory configured to add the cache line to the read set of the transaction ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the hardware transactional memory is further configured to set a first flag to a value indicating the first word. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the hardware transactional memory is further configured to read the first flag to determine if the second word is the same as the first word. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein the hardware transactional memory is further configured to set, in response to the second word being not the same as the first word, a second flag to a value indicating that the first word and the second word have been speculatively read during the transaction. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the hardware transactional memory is further configured to read the second flag. ### Claim 19 (depends on 14) The apparatus of claim 14, wherein the hardware transactional memory is further configured to set an SR bit of the cache line. ### Claim 20 (depends on 14) The apparatus of claim 14, wherein the hardware transactional memory is configured to set the first flag to a binary value according to a 0-indexing scheme. ### Claim 21 (depends on 14) The apparatus of claim 14, further comprising a Bloom filter configured to store at least one of the first flag or the second flag. ### Claim 22 (depends on 21) The apparatus of claim 21, wherein the hardware transactional memory is further configured to apply a hash function to the address of the first word or the second word. ### Claim 23 (depends on 22) The apparatus of claim 22, wherein the hash function is a modulo function. ### Claim 24 (depends on 23) The apparatus of claim 23, wherein the Bloom filter has a number of indices M, and the hardware transactional memory is further configured to derive an identifier for the address by shifting the address by log2(M) bits. ### Claim 25 A non-transitory computer readable storage medium comprising a data structure which is operated upon by a program executable on a computer system, the program operating on the data structure to perform a portion of a process to fabricate an integrated circuit including circuitry described by the data structure, the circuitry described in the data structure including: a processor configured to enter a speculative execution mode, speculatively read a first word in a cache line as part of a transaction, speculatively read a second word in the cache line as part of the transaction, detect an instruction specifying release of at least one of the first word and the second word from a read set; and prevent the release of the at least one of the first word and the second word from the read set when the first word and the second word are not the same word. ### Claim 26 (depends on 25) The non-transitory computer readable storage of claim 25, wherein the circuitry further includes: a hardware transactional memory configured to add the cache line to the read set of the transaction. ### Claim 27 (depends on 26) The non-transitory computer readable storage of claim 26, wherein the hardware transactional memory is further configured to set a first flag to a value indicating the first word. ### Claim 28 (depends on 27) The non-transitory computer readable storage of claim 27, wherein the hardware transactional memory is further configured to; read the first flag to determine if the second word is the same as the first word. ### Claim 29 (depends on 28) The non-transitory computer readable storage of claim 28, wherein the hardware transactional memory is further configured toset, in response to the second word being not the same as the first word, a second flag to a value indicating that the first word and the second word have been speculatively read during the transaction. ### Claim 30 (depends on 29) The non-transitory computer readable storage of claim 29, wherein the hardware transactional memory is further configured to read the second flag. ### Claim 31 The non-transitory computer readable storage medium of 25, wherein the storage medium stores HDL, Verilog, or GDSII data.