# US 8,543,774 B2 · Programmable logic apparatus employing shared memory, vital processor and non-vital communications processor, and system including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,774 B2 - Document ID: US8543774B2 - Status: Granted - Kind: B2 - Application number: 13/079,962 - Filed: 2011-04-05 - Published: 2012-10-11 - Granted: 2013-09-24 - Earliest claimed: 2011-04-05 - Assignees: Ansaldo STS USA, Inc. - Applicants: John E. Lemonovich; William A. Sharp - Inventors: John E. Lemonovich; William A. Sharp - Web page: https://patentgrep.com/patent/US8543774B2 ## CPC - G06F 15/17: using an input/output type connection, e.g. channel, I/O port - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A programmable logic apparatus includes a shared memory having a first port, a second port and a third port; a first vital processor interfaced to the first port of the shared memory; and a non-vital communications processor separated from the first vital processor in the programmable logic apparatus and interfaced to the second port of the shared memory. The third port of the shared memory is an external port structured to interface an external second vital processor. ## Claims ### Claim 1 A programmable logic apparatus comprising: a shared memory comprising a first port, a second port and a third port; a first vital processor interfaced to the first port of said shared memory; and a non-vital communications processor separated from said first vital processor in said programmable logic apparatus and interfaced to the second port of said shared memory, wherein the third port of said shared memory is an external port structured to interface an external second vital processor, wherein said shared memory further comprises a first memory and a second memory; wherein each of said first memory and said second memory comprises a first port and a second port; wherein the first ports of the first memory and the second memory are part of the second port of said shared memory; wherein the second port of the first memory is part of the first and third ports of said shared memory; wherein the second port of the second memory is part of the first and third ports of said shared memory; and wherein both of said first vital processor and said external second vital processor are structured to cooperatively agree that first data in said first memory corresponds to second data in said second memory, and responsively cause said non-vital communications processor to employ part of said first data and part of said second data as third data, and to output serial data based upon said third data. ### Claim 2 (depends on 1) The programmable logic apparatus of claim 1 wherein said programmable logic apparatus is a single field programmable gate array. ### Claim 3 (depends on 1) The programmable logic apparatus of claim 1 wherein said non-vital communications processor is structured to communicate with at least one of an interlocking controller using a peer protocol or a master/slave protocol, a partner track circuit, a configuration data storage device, and a user interface. ### Claim 4 A programmable logic apparatus comprising: a shared memory comprising a first port, a second port and a third port; a first vital processor interfaced to the first port of said shared memory; and a non-vital communications processor separated from said first vital processor in said programmable logic apparatus and interfaced to the second port of said shared memory, wherein the third port of said shared memory is an external port structured to interface an external second vital processor, wherein said shared memory comprises a first memory, a second memory, a third memory and a fourth memory; wherein each of said first memory, said second memory, said third memory and said fourth memory comprises a first port and a second port; wherein the first ports of the first memory, the second memory, the third memory and the fourth memory are part of the second port of said shared memory; wherein the second port of the first memory is part of the first port of said shared memory; wherein the second port of the second memory is part of the first and third ports of said shared memory; wherein the second port of the third memory is part of the first and third ports of said shared memory; and wherein the second port of the fourth memory is part of the third port of said shared memory. ### Claim 5 (depends on 4) The programmable logic apparatus of claim 4 wherein the first ports of the first memory, the second memory, the third memory and the fourth memory are structured to permit read or write operations by said non-vital communications processor; wherein the second port of the first memory is structured to permit read or write operations by said first vital processor; wherein the second port of the second memory is structured to permit write operations by said first vital processor and read operations by said external second vital processor; wherein the second port of the third memory is structured to permit read operations by said first vital processor and write operations by said external second vital processor; and wherein the second port of the fourth memory is structured to permit read or write operations by said external second vital processor. ### Claim 6 (depends on 4) The programmable logic apparatus of claim 4 wherein both of said first vital processor and said external second vital processor are structured to cooperatively agree that first data in said second memory corresponds to second data in said third memory, and responsively cause said non-vital communications processor to employ: (a) one of said first data and said second data as third data, or (b) part of said first data and part of said second data as said third data, and to output serial data based upon said third data. ### Claim 7 (depends on 1) The programmable logic apparatus of claim 1 wherein said first vital processor is diverse with respect to said external second vital processor. ### Claim 8 (depends on 7) The programmable logic apparatus of claim 7 wherein said external second vital processor is a field programmable gate array. ### Claim 9 (depends on 1) The programmable logic apparatus of claim 1 wherein said external second vital processor is a field programmable gate array. ### Claim 10 (depends on 1) The programmable logic apparatus of claim 1 wherein said shared memory separates said first vital processor from said non-vital communications processor. ### Claim 11 A system comprising: a programmable logic apparatus comprising: a shared memory comprising a first port, a second port and a third port, a first vital processor interfaced to the first port of said shared memory, and a non-vital communications processor separated from said first vital processor in said programmable logic apparatus and interfaced to the second port of said shared memory; and a second vital processor external to said programmable logic apparatus, wherein the third port of said shared memory is an external port interfacing said second vital processor, wherein said shared memory further comprises a first memory and a second memory; wherein each of said first memory and said second memory comprises a first port and a second port; wherein the first ports of the first memory and the second memory are part of the second port of said shared memory; wherein the second port of the first memory is part of the first and third ports of said shared memory; wherein the second port of the second memory is part of the first and third ports of said shared memory; and wherein both of said first vital processor and said second vital processor are structured to cooperatively agree that first data in said first memory corresponds to second data in said second memory, and responsively cause said non-vital communications processor to employ part of said first data and part of said second data as third data and to output serial data based upon said third data. ### Claim 12 (depends on 11) The system of claim 11 wherein said programmable logic apparatus is a single field programmable gate array. ### Claim 13 (depends on 11) The system of claim 11 wherein said non-vital communications processor is structured to communicate with at least one of an interlocking controller using a peer protocol or a master/slave protocol, a partner track circuit, a configuration data storage device, and a user interface. ### Claim 14 A system comprising: a programmable logic apparatus comprising: a shared memory comprising a first port, a second port and a third port, a first vital processor interfaced to the first port of said shared memory, and a non-vital communications processor separated from said first vital processor in said programmable logic apparatus and interfaced to the second port of said shared memory; and a second vital processor external to said programmable logic apparatus, wherein the third port of said shared memory is an external port interfacing said second vital processor, wherein said shared memory comprises a first memory, a second memory, a third memory and a fourth memory; wherein each of said first memory, said second memory, said third memory and said fourth memory comprises a first port and a second port; wherein the first ports of the first memory, the second memory, the third memory and the fourth memory are part of the second port of said shared memory; wherein the second port of the first memory is part of the first port of said shared memory; wherein the second port of the second memory is part of the first and third ports of said shared memory; wherein the second port of the third memory is part of the first and third ports of said shared memory; and wherein the second port of the fourth memory is part of the third port of said shared memory. ### Claim 15 (depends on 14) The system of claim 14 wherein the first ports of the first memory, the second memory, the third memory and the fourth memory are structured to permit read or write operations by said non-vital communications processor; wherein the second port of the first memory is structured to permit read or write operations by said first vital processor; wherein the second port of the second memory is structured to permit write operations by said first vital processor and read operations by said second vital processor; wherein the second port of the third memory is structured to permit read operations by said first vital processor and write operations by said second vital processor; and wherein the second port of the fourth memory is structured to permit read or write operations by said second vital processor. ### Claim 16 (depends on 11) The system of claim 11 wherein said first vital processor is diverse with respect to said second vital processor. ### Claim 17 (depends on 16) The system of claim 16 wherein said second vital processor is a field programmable gate array. ### Claim 18 (depends on 11) The system of claim 11 wherein said second vital processor is a field programmable gate array. ### Claim 19 (depends on 11) The system of claim 11 wherein said shared memory separates said first vital processor from said non-vital communications processor. ### Claim 20 (depends on 11) The system of claim 11 wherein said programmable logic apparatus is a first field programmable gate array; and wherein said second vital processor is a separate second field programmable gate array.