# US 8,543,765 B2 · Efficient data prefetching in the presence of load hits > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,765 B2 - Document ID: US8543765B2 - Status: Granted - Kind: B2 - Application number: 13/535,188 - Filed: 2012-06-27 - Published: 2012-10-25 - Granted: 2013-09-24 - Earliest claimed: 2009-07-10 - Assignees: VIA Technologies, Inc. - Applicants: Clinton Thomas Glover; Colin Eddy; Rodney E. Hooker; Albert J. Loper - Inventors: Clinton Thomas Glover; Colin Eddy; Rodney E. Hooker; Albert J. Loper - Web page: https://patentgrep.com/patent/US8543765B2 ## CPC - G06F 12/0862: with prefetch - G06F 12/0859: {with reload from main memory} - G06F 12/0897: with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) - G06F 2212/6022: Using a prefetch buffer or dedicated prefetch cache - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory subsystem in a microprocessor includes a first-level cache, a second-level cache, and a prefetch cache configured to speculatively prefetch cache lines from a memory external to the microprocessor. The second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both. If a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache. ## Claims ### Claim 1 A method for caching data in a memory subsystem in a microprocessor configured to access an external memory, the memory subsystem having a first-level cache, a second-level cache, and a prefetch cache, configured to speculatively prefetch cache lines from a memory external to the microprocessor, the method comprising: allowing, by the second-level cache and the prefetch cache, the same cache line to be simultaneously present in both the second-level cache and the prefetch cache; determining whether a request by the first-level cache for the cache line hits in both the second-level cache and in the prefetch cache; and if the request hits in both the second-level cache and in the prefetch cache: invalidating, by the prefetch cache, its copy of the cache line; and providing, by the second-level cache, the cache line to the first-level cache. ### Claim 2 (depends on 1) The method of claim 1, further comprising: providing collectively, by the second-level cache and the prefetch cache, a single response to the first-level cache request. ### Claim 3 (depends on 1) The method of claim 1, further comprising: concurrently processing, by an identical number of pipeline stages of each of the second-level cache and the prefetch cache in the same sequence, the request by the first-level cache. ### Claim 4 (depends on 1) The method of claim 1, further comprising: if the request hits in only the prefetch cache: providing, by the prefetch cache, the cache line to the second-level cache; and providing, by the second-level cache, the cache line to the first-level cache. ### Claim 5 (depends on 1) The method of claim 1, further comprising: prefetching, by the prefetch cache, a cache line from the external memory without querying the second-level cache for the status of the cache line. ### Claim 6 A memory subsystem in a microprocessor, comprising: a first-level cache; a second-level cache; and a prefetch cache, configured to speculatively prefetch cache lines from a memory external to the microprocessor; wherein the second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both; wherein if a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache. ### Claim 7 (depends on 6) The memory subsystem of claim 6, wherein the second-level cache and the prefetch cache collectively provide a single response to the first-level cache request. ### Claim 8 (depends on 6) The memory subsystem of claim 6, wherein the second-level cache and the prefetch cache are configured with an identical number of pipeline stages that concurrently process the request by the first-level cache in the same sequence. ### Claim 9 (depends on 6) The memory subsystem of claim 6, wherein if the request hits in only the prefetch cache, the prefetch cache provides the cache line to the second-level cache and the second-level cache provides the cache line to the first-level cache. ### Claim 10 (depends on 6) The memory subsystem of claim 6, wherein the prefetch cache is configured to prefetch a cache line from the external memory without querying the second-level cache for the status of the cache line. ### Claim 11 A computer program product encoded in at least one non-transitory, tangible computer readable storage medium for use with a computing device, the computer program product comprising: computer readable program code embodied in said medium, for specifying a memory subsystem in a microprocessor, the computer readable program code comprising: first program code for specifying a first-level cache; second program code for specifying a second-level cache; and third program code for specifying a prefetch cache, configured to speculatively prefetch cache lines from a memory external to the microprocessor; wherein the second-level cache and the prefetch cache are configured to allow the same cache line to be simultaneously present in both; wherein if a request by the first-level cache for a cache line hits in both the second-level cache and in the prefetch cache, the prefetch cache invalidates its copy of the cache line and the second-level cache provides the cache line to the first-level cache. ### Claim 12 (depends on 11) The computer program product of claim 11, wherein the second-level cache and the prefetch cache collectively provide a single response to the first-level cache request. ### Claim 13 (depends on 11) The computer program product of claim 11, wherein the second-level cache and the prefetch cache are configured with an identical number of pipeline stages that concurrently process the request by the first-level cache in the same sequence. ### Claim 14 (depends on 11) The computer program product of claim 11, wherein if the request hits in only the prefetch cache, the prefetch cache provides the cache line to the second-level cache and the second-level cache provides the cache line to the first-level cache. ### Claim 15 (depends on 11) The computer program product of claim 11, wherein the prefetch cache is configured to prefetch a cache line from the external memory without querying the second-level cache for the status of the cache line. ### Claim 16 (depends on 11) The computer program product of claim 11, wherein the at least one computer readable storage medium is selected from the set of a disk, tape, or other magnetic, optical, or electronic storage.