# US 8,543,758 B2 · Apparatus including memory channel control circuit and related methods for relaying commands to logical units > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,758 B2 - Document ID: US8543758B2 - Status: Granted - Kind: B2 - Application number: 13/149,461 - Filed: 2011-05-31 - Published: 2012-12-06 - Granted: 2013-09-24 - Earliest claimed: 2011-05-31 - Assignees: Micron Technology, Inc. - Applicants: Douglas A. Larson; Jeffrey R. Brown - Inventors: Douglas A. Larson; Jeffrey R. Brown - Web page: https://patentgrep.com/patent/US8543758B2 ## CPC - G06F 12/0246: {in block erasable memory, e.g. flash memory} - G06F 3/0613: {in relation to throughput} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]} - G11C 16/06: Auxiliary circuits, e.g. for writing into memory - G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units. ## Claims ### Claim 1 A method, comprising: relaying a first plurality of commands for a particular logical unit via a logical unit request queue (LRQ) in a channel control circuit to one of a plurality of logical unit command queues (LCQs) in an order that the first plurality of commands were received, wherein the plurality of LCQs are coupled to the LRQ and are associated with the particular logical unit; relaying a second plurality of commands for different logical units via the LRQ to those of the plurality of LCQs associated with the different logical units in an order according to a status of the different logical units; queuing, with the LRQ, a first command for a particular logical unit in response to the LCQ associated with the particular logical unit being full; receiving, with a channel request queue (CRQ) coupled to the channel control circuit, a second command from the switch and relaying the second command to the LRQ; and queuing, with the CRQ, a third command for the LRQ in response to the LRQ being full. ### Claim 2 (depends on 1) The method of claim 1, wherein the method includes: receiving the first plurality of commands from a switch at the CRQ and relaying the first plurality of commands to the LRQ; and receiving the second plurality of commands from the switch at the CRQ and relaying the second plurality of commands to the LRQ. ### Claim 3 (depends on 1) The method of claim 1, wherein the status of the different logical units is a ready/busy status, and wherein the method includes: relaying a first one of the second plurality of commands to a first LCQ before relaying the second one of the second plurality of commands to a second LCQ in response to the status of the different logical unit associated with the second LCQ being busy, wherein the first one of the second plurality of commands is received later in time than the second one of the second plurality of commands; and relaying the second one of the second plurality of commands to the second LCQ in response to the status of the associated different logical unit being ready. ### Claim 4 An apparatus, comprising: a switch; and non-volatile memory control circuitry coupled to the switch, wherein the non-volatile memory control circuitry includes: a plurality of channel control circuits, wherein each of the plurality of channel control circuits include: a plurality of logical unit command queues (LCQs); and a logical unit request queue (LRQ) coupled to the plurality of LCQs, wherein the LRQ is configured to: relay a first plurality of commands for a first particular logical unit to one of the plurality of LCQs associated with the first particular logical unit in an order that the first plurality of commands were received; relay a second plurality of commands for different logical units to those of the LCQs associated with the different logical units in an order according to a status of the different logical units; and queue a first command for a second particular logical unit in response to the LCQ associated with the second particular logical unit being full; and a channel request queue (CRQ) coupled to the plurality of channel control circuits, wherein the CRQ is configured to: receive a second command from the switch and relay the second command to one of the LRQs; and queue a third command for a particular LRQ in response to the particular LRQ being full. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein: the status of the different logical units is a ready/busy status of the different logical units; and the LRQ is configured to relay a first one of the second plurality of commands to a first LCQ before relaying the second one of the second plurality of commands to a second LCQ in response to the status of the different logical unit associated with the second LCQ being busy, wherein the first one of the second plurality of commands is received later in time than the second one of the second plurality of commands. ### Claim 6 (depends on 5) The apparatus of claim 5, wherein the LRQ is configured to relay the second one of the second plurality of commands to the second LCQ in response to the status of the associated different logical unit being ready. ### Claim 7 (depends on 4) The apparatus controller of claim 4, wherein each channel control circuit is configured to be coupled to a plurality of logical units by an Open NAND Flash Interface (ONFI) compliant bus. ### Claim 8 (depends on 4) The apparatus of claim 4, wherein each of the plurality of LCQs comprises a 2-deep first-in-first-out (FIFO) circuit configured to queue a current command and a next command to be executed subsequent to the current command, and wherein each of the plurality of LCQs is configured to be coupled to a different logical unit. ### Claim 9 (depends on 4) The apparatus of claim 4, wherein the LRQ comprises an L-number-deep queue circuit, where L is equal to a number of logical units per channel control circuit. ### Claim 10 (depends on 4) The apparatus of claim 4, wherein the CRQ comprises a C-number-deep queue circuit, where C is equal to x*(the plurality of channel control circuits), where x is a whole number. ### Claim 11 An apparatus, comprising: a switch; and non-volatile memory control circuitry coupled to the switch, wherein the non-volatile memory control circuitry includes: a plurality of channel control circuits, wherein each of the plurality of channel control circuits include: a plurality of logical unit command queues (LCQs); and a logical unit request queue (LRQ) coupled to the plurality of LCQs, wherein the LRQ comprises an L-number-deep queue circuit, where L is equal to a number of logical units per channel control circuit, and wherein the LRQ is configured to: relay a first plurality of commands for a particular logical unit to one of the plurality of LCQs associated with the particular logical unit in an order that the first plurality of commands were received; and relay a second plurality of commands for different logical units to those of the LCQs associated with the different logical units in an order according to a status of the different logical units; and a channel request queue (CRQ) coupled to the plurality of channel control circuits, wherein the CRQ is configured to receive a command from the switch and relay the command to one of the LRQs. ### Claim 12 (depends on 11) The apparatus of claim 11, wherein: the status of the different logical units is a ready/busy status of the different logical units; and the LRQ is configured to relay a first one of the second plurality of commands to a first LCQ before relaying the second one of the second plurality of commands to a second LCQ in response to the status of the different logical unit associated with the second LCQ being busy, wherein the first one of the second plurality of commands is received later in time than the second one of the second plurality of commands. ### Claim 13 (depends on 11) The apparatus of claim 11, wherein the LRQ is configured to relay the second one of the second plurality of commands to the second LCQ in response to the status of the associated different logical unit being ready. ### Claim 14 (depends on 11) The apparatus controller of claim 11, wherein each channel control circuit is configured to be coupled to a plurality of logical units by an Open NAND Flash Interface (ONFI) compliant bus. ### Claim 15 (depends on 11) The apparatus of claim 11, wherein each of the plurality of LCQs comprises a 2-deep first-in-first-out (FIFO) circuit configured to queue a current command and a next command to be executed subsequent to the current command, and wherein each of the plurality of LCQs is configured to be coupled to a different logical unit. ### Claim 16 An apparatus, comprising: a switch; and non-volatile memory control circuitry coupled to the switch, wherein the non-volatile memory control circuitry includes: a plurality of channel control circuits, wherein each of the plurality of channel control circuits include: a plurality of logical unit command queues (LCQs); and a logical unit request queue (LRQ) coupled to the plurality of LCQs, wherein the LRQ is configured to: relay a first plurality of commands for a particular logical unit to one of the plurality of LCQs associated with the particular logical unit in an order that the first plurality of commands were received; and relay a second plurality of commands for different logical units to those of the LCQs associated with the different logical units in an order according to a status of the different logical units; and a channel request queue (CRQ) coupled to the plurality of channel control circuits, wherein the CRQ comprises a C-number-deep queue circuit, where C is equal to x*(the plurality of channel control circuits), where x is a whole number, and wherein the CRQ is configured to receive a command from the switch and relay the command to one of the LRQs. ### Claim 17 (depends on 16) The apparatus of claim 16, wherein: the status of the different logical units is a ready/busy status of the different logical units; and the LRQ is configured to relay a first one of the second plurality of commands to a first LCQ before relaying the second one of the second plurality of commands to a second LCQ in response to the status of the different logical unit associated with the second LCQ being busy, wherein the first one of the second plurality of commands is received later in time than the second one of the second plurality of commands. ### Claim 18 (depends on 16) The apparatus of claim 16, wherein the LRQ is configured to relay the second one of the second plurality of commands to the second LCQ in response to the status of the associated different logical unit being ready. ### Claim 19 (depends on 16) The apparatus controller of claim 16, wherein each channel control circuit is configured to be coupled to a plurality of logical units by an Open NAND Flash Interface (ONFI) compliant bus. ### Claim 20 (depends on 16) The apparatus of claim 16, wherein each of the plurality of LCQs comprises a 2-deep first-in-first-out (FIFO) circuit configured to queue a current command and a next command to be executed subsequent to the current command, and wherein each of the plurality of LCQs is configured to be coupled to a different logical unit.