# US 8,543,753 B2 · Multi-use physical architecture

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- Number: US 8,543,753 B2
- Document ID: US8543753B2
- Status: Granted
- Kind: B2
- Application number: 13/080,799
- Filed: 2011-04-06
- Published: 2012-10-11
- Granted: 2013-09-24
- Earliest claimed: 2011-04-06
- Assignees: International Business Machines Corporation
- Applicants: Daniel M. Dreps; Kyu-hyoun Kim; Michael A. Sorna; Glen A. Wiedemeier
- Inventors: Daniel M. Dreps; Kyu-hyoun Kim; Michael A. Sorna; Glen A. Wiedemeier
- Web page: https://patentgrep.com/patent/US8543753B2

## CPC

- G06F 13/385: {for adaptation of a particular data processing system to different peripheral devices}
- G06F 13/4072: {Drivers or receivers (G06F13/4086 takes precedence; for multistate logic circuits H03K19/0002)}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1066: {Output synchronization}
- G11C 7/1093: {Input synchronization}
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A multi-use physical (PHY) architecture that includes a PHY connection that includes one or more bit lines and that is communicatively coupled to a first processor. The PHY connection is configurable to carry signals between the first processor and a second processor, or between the first processor and a memory. The one or more bit lines are configured to carry signals bi-directionally at a first voltage when the PHY connection is configured to carry signals between the first processor and the memory. The one or more bit lines are configured to carry signals uni-directionally at a second voltage when the PHY connection is configured to carry signals between the first processor and the second processor. The second voltage is different than the first voltage.

## Claims

### Claim 1

A multi-use physical (PHY) architecture comprising:
a PHY connection including one or more bit lines, the PHY connection communicatively coupled to a first processor;
the PHY connection configurable to carry signals between the first processor and a second processor, or between the first processor and a memory;
the one or more bit lines configured to carry signals bi-directionally at a first voltage in a first setting for the PHY connection when the PHY connection is configured to carry signals between the first processor and the memory, wherein data is transferred over the one or more bit lines using a bursting strobe signal; and
the one or more bit lines configured to carry signals uni-directionally at a second voltage in a second setting for the PHY connection when the PHY connection is configured to carry signals between the first processor and the second processor, wherein data is transferred over the one or more bit lines using a continuous clock signal and the second voltage different than the first voltage.

### Claim 2 (depends on 1)

The multi-use PHY architecture of claim 1, wherein the PHY connection is configured using only software.

### Claim 3 (depends on 1)

The multi-use PHY architecture of claim 1, wherein the memory is double data rate four (DDR4) memory.

### Claim 4 (depends on 1)

The multi-use PHY architecture of claim 1, wherein the memory is double data rate three (DDR3).

### Claim 5 (depends on 1)

The multi-use PHY architecture of claim 1, wherein a single oxide is used for communication to both the memory and the second processor.

### Claim 6 (depends on 1)

The multi-use PHY architecture of claim 1, wherein the PHY connection is configured to switch between the bursting strobe signal and the continuous clock signal in software.

### Claim 7 (depends on 1)

The multi-use PHY architecture of claim 1, wherein the one or more bit lines are configured to carry signals uni-directionally by disabling a data query driver.

### Claim 8 (depends on 1)

The multi-use PHY architecture of claim 1, wherein the one or more bit lines are configured to carry signals uni-directionally by disabling a data query receiver.

### Claim 9

A computer implemented method for configuring a multi-use physical (PHY) connection including comprising:
determining if the multi-use PHY connection connects a first processor to a memory or to a second processor;
configuring, via a system programming module, the multi-use PHY connection, the configuring comprising:
setting one or more bit lines to carry signals uni-directionally in response to determining that the multi-use PHY connection connects the first processor to the second processor, wherein data is transferred over the one or more bit lines using a bursting strobe signal in a first setting for the PHY connection connecting the first processor to the second processor; and
setting the one or more bit lines to carry signals bi-directionally in response to determining that the multi-use PHY connection connects the first processor to the memory wherein data is transferred over the one or more bit lines using a continuous clock signal in a second setting for the PHY connection connecting the first processor to the memory.

### Claim 10 (depends on 9)

The method of claim 9, wherein the multi-use PHY connection is configured to switch between the bursting strobe signal and the continuous clock signal in software.

### Claim 11

A multi-use physical (PHY) connection including:
a first pad communicatively coupled to a second pad via one or more bit lines, the first pad communicatively coupled to a first processor;
the first pad configurable to carry signals between the first processor and the second pad, the second pad communicatively coupled to a second processor or to a memory;
the one or more bit lines configured to carry signals bi-directionally at a first voltage in a first setting for the second pad when the second pad is communicatively coupled to the memory, wherein data is transferred over the one or more bit lines using bursting strobe signal; and
the one or more bit lines configured to carry signals uni-directionally at a second voltage in a second setting for the second pad when the second pad is communicatively coupled to the second processor, wherein data is transferred over the one or more bit lines using a continuous clock signal and the second voltage is different than the first voltage.

### Claim 12 (depends on 11)

The multi-use PHY connection of claim 11, wherein the first pad is configured using only software.

### Claim 13 (depends on 11)

The multi-use PHY connection of claim 11, wherein the memory is double data rate four (DDR4) memory.

### Claim 14 (depends on 11)

The multi-use PHY connection of claim 11, wherein the memory is double data rate three (DDR3).

### Claim 15 (depends on 11)

The multi-use PHY connection of claim 11, wherein a single oxide is used for communication to both the memory and the second processor.

### Claim 16 (depends on 11)

The multi-use PHY connection of claim 11, wherein the first pad is configured to switch between the bursting strobe signal and the continuous clock signal in software.

### Claim 17 (depends on 11)

The multi-use PHY connection of claim 11, wherein the one or more bit lines are configured to carry signals uni-directionally by disabling one or both of a data query driver and a data query receiver.