# US 8,543,736 B2 · Data processing circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 8,543,736 B2 - Document ID: US8543736B2 - Status: Granted - Kind: B2 - Application number: 12/877,442 - Filed: 2010-09-08 - Published: 2011-04-21 - Granted: 2013-09-24 - Earliest claimed: 2009-10-21 - Assignees: Etron Technology, Inc. - Applicants: Chien-Chou Chen; Ming-Sung Huang; Wen Min Lu - Inventors: Chien-Chou Chen; Ming-Sung Huang; Wen Min Lu - Web page: https://patentgrep.com/patent/US8543736B2 ## CPC - G06F 7/22: Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A data processing circuit is disclosed in the present invention. The data processing circuit includes a decoder and a number of N-stage circuits. The circuits receive input data from at least a memory and separate the input data into N stages. The circuit process and store the N input data simultaneously to decrease the time of data processing in the data processing circuit. ## Claims ### Claim 1 A data processing circuit, comprising: a decoder, for decoding data; and at least three-stage circuits for receiving input data from at least a memory to output the generated output data to the decoder wherein the input data comprise a first set of data, a second set of data, and a third set of data; and the at least three-stage circuits comprise: a first-stage circuit, for sorting the input data according to the values of the input data and outputting the data with the same value to the decoder according to their order wherein the first-stage circuit outputs the first set of data having the first priority to the decoder and then the decoder generates a first data length according to the first set of data; the first-stage circuit outputs the second set of data having the second priority to the decoder according to the first data length and then the decoder generates a second data length according to the second set of data; the first-stage circuit outputs the third set of data having the third priority to the decoder according to the second data length and then the decoder generates a third data length according to the third set of data; and the decoder calculates the sum of the first data length, the second data length, and the third data length to generate a total effective bit length; a second-stage circuit, for replenishing data having a bit length equal to the total effective bit length from a third-stage circuit to the first-stage circuit according to the total effective bit length; and the third-stage circuit, for supplying data to the second-stage circuit to replenish data to reach a bit length equal to the total effective bit length and determining whether the third-stage circuit stores enough data to supply to the second-stage circuit according to the total effective bit length and determining whether the third-stage circuit receives data from the memory. ### Claim 2 (depends on 1) The circuit according to claim 1, wherein the three-stage circuits are used to sort, temporarily store, or convert the input data. ### Claim 3 (depends on 1) The circuit according to claim 1, wherein the first-stage circuit comprises: a third multiplexer, thr receiving and sorting the input data; a first buffer, for receiving and temporarily storing the input data and outputting the first set of data to the decoder; a first multiplexer, for receiving the second set of data according to the first data length and outputting the second set of data to the decoder; and a second multiplexer, for receiving the third set of data according to the second data length and outputting the third set of data to the decoder; wherein the third multiplexer further receives the data transmitted from the second-stage circuit according to the total effective bit length. ### Claim 4 (depends on 3) The circuit according to claim 3, wherein the first multiplexer is a 10-to-1 multiplexer, the second multiplexer is a 19-to-1 multiplexer, the third multiplexer is a 29-to-1 multiplexer, and the first buffer is a 32-bit first in first out (FIFO) buffer. ### Claim 5 (depends on 3) The circuit according to claim 3, wherein the first buffer further transmits the remained data after the previous processing on the three sets of data to the third multiplexer so that the remained data are sorted together with the input data to be processed next time and outputted to the first buffer. ### Claim 6 (depends on 3) The circuit according to claim 3, wherein the second-stage circuit comprises a fourth multiplexer for receiving the data transmitted by the third-stage circuit according to a first control signal where the first control signal is related to the total effective bit length of the previous processing and the first control signal of the previous processing. ### Claim 7 (depends on 6) The circuit according to claim 6, wherein the fourth multiplexer is a 32-to-1 multiplexer. ### Claim 8 (depends on 6) The circuit according to claim 6, wherein the third-stage circuit comprises: a second buffer, for temporarily storing the first portion of the input data; a third buffer, for temporarily storing the second portion of the input data wherein the second portion of the input data is placed behind the first portion of the input data; a fourth buffer, for temporarily storing the third portion of the input data wherein the third portion of the input data is placed behind the second portion of the input data; a sixth multiplexer, for receiving the input data and the remained data in the first buffer, the second buffer, or the third buffer after the previous processing and outputting the input data and/or the remained data after the previous processing according to a second control signal wherein the second control signal is related to the total effective bit length of the previous processing and the second control signal of the previous processing; and a fifth multiplexer, for deciding to output any portion of the three portions of data according to a third control signal wherein the third control signal is related to the second control signal. ### Claim 9 (depends on 8) The circuit according to claim 8, wherein the second buffer, the third buffer, and the fourth buffer are 32-bit first in first out (FIFO) buffers; the fifth multiplexer is a 3-to-1 multiplexer; and the sixth multiplexer is a 2-to-1 multiplexer. ### Claim 10 (depends on 1) The circuit according to claim 1, being a 32-to-24-bit data decoding circuit. ### Claim 11 A data processing circuit, for receiving and decoding data from a memory, the circuit comprising: a first data processing unit, for receiving data from the lowest address and sorting and decoding the data received sequentially from the lowest address to the highest address to generate first decoded data; and a second data processing unit, for receiving data from the highest address and sorting and decoding the data received sequentially from the highest address to the lowest address to generate second decoded data; wherein the first data processing unit and the second data processing unit operate simultaneously; wherein the first data processing unit or the second data processing unit comprises: a decoder, for decoding data; and at least three-stage circuits for receiving input data from at least a memory to output the generated output data to the decoder wherein the input data comprise a set of data, a second set of data, and a third set of data; and the at least three-stage circuits comprise: a first-stage circuit, for sorting the input data according to the values of the input data and outputting the data with the same value to the decoder according to their order wherein the first-stage circuit outputs the first set of data having the first priority to the decoder and then the decoder generates a first data length according to the first set of data; the first-stage circuit outputs the second set of data having the second priority to the decoder according to the first data length and then the decoder generates a second data length according to the second set of data; the first-stage circuit outputs the third set of data having the third priority to the decoder according to the second data length and then the decoder generates a third data length according to the third set of data; and the decoder calculates the sum of the first data length, the second data length, and the third data length to generate a total effective bit length; a second-stage circuit, for replenishing data having a bit length equal to the total effective bit length from a third-stage circuit to the first-stage circuit according to the total effective bit length; and the third-stage circuit, for supplying data to the second-stage circuit to replenish data to reach a bit length equal to the total effective bit length and determining whether the third-stage circuit stores enough data to supply to the second-stage circuit according to the total effective bit length and determining whether the third-stage circuit receives data from the memory. ### Claim 12 (depends on 11) The circuit according to claim 11, wherein the data quantity at the junction between two data receiving paths of the first data processing unit and the second data processing unit is different when the sorting or processing speeds of the first data processing unit and the second data processing unit are different and the data processing circuit adds up the final remained data of the two paths to fill in an address. ### Claim 13 (depends on 11) The circuit according to claim 11, being a 32-to-24-bit data decoding circuit.